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1 datasheet digital dc/dc pmbus 10a power module zl9010m the zl9010m is a 10a adjustable output, step-down synchronous pmbus-compliant digital power supply. included in the module is a high-performance digital pwm controller, power mosfets, an inductor and all the passive components required for a highly integrated dc/dc power solution. this power module has built-in auto compensation algorithms, which eliminates the need for manual compensation design work. the zl9010m operates over a wide input voltage range and supports an output voltage range of 0.6v to 3.6v, which can be set by external resistors or via pmbus. only bulk input and output capacitors are needed to finish the design. the output voltage can be precisely regulated to as low as 0.6v with 1% output voltage regulation over line, load and temperature variations. the zl9010m functions as a switch mode power supply with added benefits of auto comp ensation, programmable power management features, parametric monitoring and status reporting capabilities. the zl9010m is packaged in a thermally enhanced, compact (17.2mm x 11.45mm) and low profile (2.5mm) overmolded high-density array (hda) pa ckage module suitable for automated assembly by standard surface mount equipment. the zl9010m is rohs compliant. figure 1 represents a typical impl ementation of the zl9010m. for pmbus operation, it is recommended to tie the enable pin (en) to sgnd. features ? complete digital switch mode power supply ? auto compensating pid filter ? 1% output voltage accuracy ? external synchronization ? overcurrent/undercurrent protection ?output voltage tracking ? current sharing and phase interleaving ? programmable sequencing (delay and ramp time) ? snapshot? parametric capture ? pmbus compliant applications ?server, telecom and datacom ? industrial and medical equipment ? general purpose point-of-load related literature ? an2034 , ?configuring current sharing on the zl2004 and zl2006? figure 1. typical application circuit figure 2. small footprint package with low profile at 2.5mm v in 2x22f 16v pmbus power-good output v out 4.5v to c out enable ddc bus ext sync zl9010m sync sa scl sda v1 fb+ fb- pg ddc sgnd en r sa r set dgnd 13.2v vdd vin vout pgnd 2.5mm 1 7 . 2 m m 1 1. 4 5 m m *patent pending package january 22, 2015 fn8422.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
zl9010m 2 fn8422.2 january 22, 2015 submit document feedback table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 internal bias and input voltage considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 design trade-offs with switching frequenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 selection of the input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 selection of the output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 multi-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pmbus communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pmbus module address selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 phase spreading for a single-phase mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 start-up procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 adaptive diode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 input undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output prebias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 tracking groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 voltage margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 active current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 monitoring via pmbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 temperature monitoring using the xtemp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 snapshot parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 nonvolatile memory and device security fe atures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 thermal vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 pmbus command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 firmware revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 package outline drawing . . . . . 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zl9010m 3 fn8422.2 january 22, 2015 submit document feedback pin configuration zl9010m (32 ld hda) top view v25 v25 pg en ddc xtemp vdd vdd 1 vin sw 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a b c d e f g h j k l vout sgnd sgnd dgnd sync sa scl sda salrt fc0 v1 1 2 3 4 5 6 7 8 9 1011121314151617 v1 ss vtrk fb+ fb- test vr pgnd pad1 pad3 pad4 pad5 v25 v25 pgnd pad2 pin descriptions pin label type description a1, a2, b3, b6 v25 pwr internal 2.5v reference. it is used to power internal circuitry. a3 pg 0 power-good output. provide open-drain power-good signal. by default, the pg pin assert s if the output is within +15/-10% of the target voltage. these limits and the pola rity of the pin may be changed via the pmbus interface. a4 en i enable input. this pin is factory set as active high. pu ll-up to enable the module switching and pull-down to disable switching. if the module is controlled through pmbus command, tie a 10k resistor from this pin to sgnd to avoid this pin floating. a5 ddc i/o digital-dc bus (open drain). the ddc pin on all digital modules in one application should be connected together. this dedicated bus provides the communication channel between mo dules for features such as sequencing, fault spreading and current sharing. a pull-up resistor is required for this application. a6 xtemp i external temperature sensor input. connect to an external 2n3904 transist or with a diode configuration. see figure 26 on page 25 . a7, a8 vdd pwr controller input voltage. tie to vin directly. c1 sgnd pwr signal ground. connect to low impedance ground plane. refer to ? layout guide ? on page 26 . d1 dgnd pwr digital ground. common return for digital signals. connect to low impedance ground plane. refer to ? layout guide ? on page 26 . e1 sync i/o clock synchronization. used for synchronization to external frequency reference. see table 8 for setting switching frequency. f1 sa i serial address select pin. used to assign unique pmbus address to each module and phase spreading. f10 pgnd pwr power ground. connect to low impedance ground plane. g1 scl i/o serial clock. pmbus interface pin. h1 sda i/o serial data. pmbus interface pin. h9 vr pwr internal 5v reference. used to power internal drivers. th e current limit for the vr pin is 10ma. please consider this wh en using the vr pin for driving external circuitry.
zl9010m 4 fn8422.2 january 22, 2015 submit document feedback j1 salrt o serial alert. pmbus interface pin. k1 fc0 i mode setting. used to set the single-phase/current sharing mode, auto compensation and sync configuration. see table 9 on page 19 . l1, l2 v1 i output voltage selection pin. it is used to program the output voltage through pin-strap setting or connecting a resis tor from the v1 pin to sgnd (see table 4 ? single resistor v out setting ? on page 16) . the set voltage on this pin is the maximum allowed output voltage in pmbus programming. l3 ss i soft-start pin. set ss pin by pin-strapping or connecting a resistor to sgnd using the appropriate resistor. the pin can program the delay from when en is asserted until the output voltage starts to ramp, the output voltage ramp time during turn on/off and input undervolta ge lockout (uvlo) level (see table 6 on page 17 ). this pin can also set tracking ratio and upper track limit (see table 10 on page 22 ). l4 vtrk i tracking sense input. used to track an external voltage source. l6 fb+ i output voltage positive feedback. positive inputs of diff erential remote sense for the regulator. connect to the output rail or the regulation point of load/processor. this pin is noise sensitive. refer to ? layout guide ? on page 26 . l7 fb- i output voltage negative feedback. negative input of the differential remote sense for the regulator. connect to the negative rail or ground of the load/processor. l8 test test test pin. for factory test us e. solder down the pin for mechanical strength, but do not connect the pin. pad1 vin pwr power inputs. input voltage range: 4.5v to 13.2v. tie directly to the input rail. when the input is between 4.5v to 5 .5v, vin should be tied directly to vcc. pad2 pgnd pwr power ground. power ground pins for both input and output returns. pad3 sgnd pwr signal ground. connect to low impedance ground plane (see figure 27 on page 27 ). pad4 sw pwr switch node. use for monitoring switching frequency. sw pad should be floating or used for snubber connections. to achieve better thermal performance, the sw planes can also be used for heat removal with thermal vias connected to large inner layers (see figure 27 on page 27 ). pad5 vout pwr power output. apply output load between these pi ns and pgnd pins. output voltage range: 0.6v to 3.6v. pin descriptions (continued) pin label type description
zl9010m 5 fn8422.2 january 22, 2015 submit document feedback pinout internal circuit gl gh vcc gnd v1 vr vdd pwml scl ddc sa en pg v25 sgnd dgnd vtrk pwmh communication sda adc csa vsa supervisor temp sensor adc protection digital compensator oc/uc d-pwm pll sync out gate drive logic nlr power management ldo ldo ss mgn ov/uv current share interleave autocomp nvm vdd digital controller gate driver fb+ fb- vout vin pgnd sgnd l 3 sw 0.5h 22 22 filter l6 e1 g1 j1 f1 l7 14 14 14 a2 h9 a7 l1 l3 a4 pad 4 14 v25 b3 a8 vdd pad 5 vout h1 v1 l2 pad 1 pad 2 pad 3 v25 b6 v25 a1 d1 dgnd c1 sgnd xtemp a6 f10 pgnd a5 fc0 k1 ss l4 a3 isenb l8 2.2f
zl9010m 6 fn8422.2 january 22, 2015 submit document feedback ordering information part number ( notes 1 , 2 , 3 ) part marking firmware revision ( note 4 ) temp range (c) package (rohs compliant) pkg. dwg. # zl9010mirz zl9010m fe03 -40 to +85 32 ld 17.2x11.45 hda y32.17.2x11.45 zl9010mairz zl9010m fe04 -40 to +85 32 ld 17.2x11.45 hda y32.17.2x11.45 ZL9010MEVAL1Z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil plastic packaged products are rohs compliant by eu exemption 7c-i and employ special pb-free material sets, mo lding compounds/die attach materials, and 100% matte tin plate plus anneal (e3) term ination finish which is compatible with both snpb and pb-free s oldering operations. intersil rohs compliant products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free require ments of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for zl9010m . for more information on msl please see tech brief tb363 . 4. see ? firmware revision history ? on page 67 ; only the latest firmware revisi on is recommended for new designs. zl xxxxm f t r z s digital ? module ? designator base ? part ? number firmware ? revision blank: ? fe03 a: ? fe04 operating ? temperature i: ? industrial ? ( \? 40c ? to ? +85c) shipping ? option blank: ? bulk t: ? tape ? and ? reel rohs z: ? rohs ? compliant package ? designator r: ? quad ? flat ? no \ lead ? (qfn)
zl9010m 7 fn8422.2 january 22, 2015 submit document feedback absolute maximum ratings ( note 5 ) thermal information dc supply voltage for vdd pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v input voltage for vin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v mosfet drive reference for vr pin . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v 2.5v logic reference for v25 pin. . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3v logic i/o voltage for pg, en, ddc, sync, pg, scl, sda, salrt, fc0, v1, ss pins . . . . . . . . . . . . . . . . . -0.3v to 6v analog input voltages xtemp, vtrk, fb+, fb-, isenb pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v switch node for sw pin continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(pgnd - 0.3v) to 30v transient (<100ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pgnd - 5v) to 30v ground voltage differential (dgnd - sgnd, pgnd - sgnd) for dgnd, sgnd and pgnd pins . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c110d) . . . . . . . . . . . 1000v latch-up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 32 ld hda package ( notes 8 , 9 ) . . . . . . . . 15 1 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 28 recommended operating conditions input supply voltage range, v in . . . . . . . . . . . . . . . . . . . . . . 4.5v to 13.2v input supply for controller, v dd ( note 6 ) . . . . . . . . . . . . . . . . 4.5v to 13.2v driver supply voltage, vr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v output voltage range, v out ( note 7 ) . . . . . . . . . . . . . . . . . . . 0.54v to 3.6v output current range, i out(dc) ( note 20 ). . . . . . . . . . . . . . . . . . . 0a to 10a operating junction temperature range, t j . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. voltage measured with respect to sgnd. 6. v in supplies the power fets. v dd supplies the controller. v in can be tied to v dd . for v dd 5.5v, v dd should be tied to vr. 7. includes 10% margin limits. 8. ? ja is simulated in free air with device mounted on a four-layer fr-4 test board (76.2 x 114.3 x 1.6mm) with 80% coverage, 2oz cu on top and bottom layers, plus two, buried, one-ounce cu layers with coverage acro ss the entire test board area. mu ltiple vias were used, with vi a diameter = 0.3mm on 1.2mm pitch. 9. for ? jc , the ?case? temperature is measured at the center of the package underside. electrical specifications v in = v dd = 12v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. parameter test conditions min ( note 10 ) typ ( note 11 ) max ( note 10 )units input and supply characteristics input bias supply current, i dd v in = v dd = 13.2v, f sw = 400khz, no load ? 35 45 ma input bias shutdown current, i dds en = 0v, no pmbus activity ? 15.5 20 ma input supply current, i vin v in = 12v, i out = 10a, v out = 1.2v, f sw = 400khz ? 1.22 ? a vr reference output voltage ( note 12 )v dd > 6v 4.5 5.2 5.7 v v25 reference output voltage ( note 12 )v r > 3v 2.25 2.5 2.75 v output characteristics output voltage adjustment range ( note 12 )v in > v out . does not include margin limits. 0.6 ? 3.3 v output voltage set-point resolution set using resistors. (see table 1 ) ? 50 - 200 ? mv set using pmbus with temperature compensation applied ? 0.025 ? % fs output voltage accuracy ( notes 12 , 13 ) includes line, load, temperature -1 ? 1 % vsen input bias current ( note 12 ) vsen = 5.5v ? 110 200 a output load current ( note 20 )v in = 12v, v out = 1.2v ? 10 ? a peak-to-peak output ripple voltage, v out ( note 13 )i out = 6a, v out = 1.2v, c out = 1000f ? 20 ? mv soft-start delay duration range ( notes 12 , 14 ) set using ss pin or resistor 5 ? 20 ms set using pmbus 0.005 ? 500 s
zl9010m 8 fn8422.2 january 22, 2015 submit document feedback soft-start delay duration accuracy ( notes 12 , 14 )turn-on delay ( note 16 ) ? -0.25/+4 ? ms turn-off delay ( note 16 ) ? -0.25/+4 ? ms soft-start ramp duration range ( notes 12 , 14 ) set using ss pin or resistor 2 ? 20 ms set using 0 ? 200 ms soft-start ramp duration accuracy ( note 12 )?100?s dynamic characteristics voltage change for positive load step i out = 2a to 10a, slew rate = 1.6a/ s, v out = 1.2v (see figure 19 ) ?4?% voltage change for positive load step i out = 10a to 2a, slew rate = 1.6a/ s, v out = 1.2v (see figure 19 ) ?4?% oscillator and switching characteristics ( note 12 ) switching frequency range 300 ? 1000 khz switching frequency set-point accuracy predefined settings (see table 1 ) -5 ? 5 % maximum pwm duty cycle factory setting ( note 19 )-? 95 % minimum sync pulse width 150 ??ns input clock frequency drift tolerance external clock source -13 ? 13 % logic input/output characteristics ( note 12 ) pmbus speed ?100?khz logic input bias current en, pg, scl, sda pins -10 ? 10 a logic input low, v il ?? 0.8 v logic input high, v ih 2.0 ??v logic output low, v ol i ol 4ma ( note 18 )?? 0.4 v logic output high, v oh i oh -2ma ( note 18 ) 2.25 ??v tracking ( note 12 ) vtrk input bias current vtrk = 5.5v ? 110 200 a vtrk tracking ramp accuracy 100% tracking, v out - vtrk, no prebias -100 ? + 100 mv vtrk regulation accuracy 100% tracking, v out - vtrk -1 ? 1 % fault protection characteristics ( note 12 ) uvlo threshold range configurable via pmbus 2.85 ? 16 v uvlo set-point accuracy -150 ? 150 mv uvlo hysteresis factory setting ? 3 ? % configurable via i pmbus 0 ? 100 % uvlo delay ?? 2.5 s power-good v out threshold factory setting ?90?% v out power-good v out hysteresis factory setting ? 5 ? % power-good delay ( note 17 ) configurable via pmbus 0 ? 500 s vsen undervoltage threshold factory setting ? 85 ? % v out configurable via pmbus 0 ? 110 % v out electrical specifications v in = v dd = 12v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter test conditions min ( note 10 ) typ ( note 11 ) max ( note 10 )units
zl9010m 9 fn8422.2 january 22, 2015 submit document feedback vsen overvoltage threshold factory setting ? 115 ? % v out configurable via pmbus 0 ? 115 % v out vsen undervoltage hysteresis ?5?% v out vsen undervoltage/overvoltage fault response time factory setting ?16?s configurable via pmbus 5 ? 60 s thermal protection threshold (controller junction temperature) factory setting ? 125 ? c configurable via pmbus -40 ? 125 c thermal protection hysteresis ?15?c notes: 10. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11. parameters with typ limits are not production tested unless otherwise specified. 12. parameters are 100% tested for internal controller prior to module assembly. 13. v out measured at the termination of the fb+ and fb- sense points. 14. the device requires a delay period following an enable signal and prior to ramping its output. 15. precise ramp timing mode is only valid when using the en pin to enable the device rather than pmbus enable. 16. the devices may require up to a 4ms delay following the assert ion of the enable signal (norma l mode) or following the de-ass ertion of the enable signal. 17. factory setting for power-good delay is set to the same value as the soft-start ramp time. 18. nominal capacitance of logic pins is 5pf. 19. maximum duty cycle is limited by th e equation max_duty(%) = [1 - (15010 -9 f sw )] 100 and not to exceed 95%. 20. the load current is related to the thermal derating curves. the maximum allowed current is derated while the output voltage goes higher than 2.5v. electrical specifications v in = v dd = 12v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter test conditions min ( note 10 ) typ ( note 11 ) max ( note 10 )units
zl9010m 10 fn8422.2 january 22, 2015 submit document feedback typical performance curves operating conditions: t a = +25c, no air flow, c out = 3 x 100f + 1 x 330f. typical values are used unless otherwise noted. figure 3. zl9010m efficiency, v in = 5v figure 4. zl9010m efficiency, v in = 12v figure 5. v out = 1.2v transient response figure 6. v out = 1.8v transient response figure 7. v out = 2.5v transient response figure 8. v out = 3.3v transient response i out (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 01 2 3 4 5 6 7 8 9 10 3.3v 471khz 2.5v 615khz 1.8v 615khz 1.2v 400khz 1.0v 400khz 0.6v 400khz i out (a) efficiency (%) 40 45 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 3.3v 800khz 2.5v 800khz 1.8v 615khz 1.2v 400khz 1.0v 400khz 1.0v 400khz v in = 12v v out = 1.2v i out step = 2a to 10a slew 1.6a/s f sw = 615khz 100mv/div 2a/div 200s/div v out i out v in = 12v v out = 1.8v i out step = 2a to 10a slew 1.6a/s f sw = 615khz 100mv/div 2a/div 200s/div v out i out v in = 12v v out = 2.5v i out step = 2a to 10a slew 1.6a/s f sw = 615khz 100mv/div 2a/div 200s/div v out i out v in = 12v v out = 3.3v i out step = 2a to 10a slew 1.6a/s f sw = 800khz 100mv/div 2a/div 200s/div v out i out
zl9010m 11 fn8422.2 january 22, 2015 submit document feedback figure 9. v out = 1.2v output voltage ripple figure 10. v out = 1.8v output voltage ripple figure 11. v out = 2.5v output voltage ripple figure 12. v out = 3.3v output voltage ripple figure 13. soft-stop ramp-down figure 14. soft-start ramp-up typical performance curves operating conditions: t a = +25c, no air flow, c out = 3 x 100f + 1 x 330f. typical values are used unless otherwise noted. (continued) v in = 12v v out = 1.2v f sw = 615khz 20mv/div 20mv/div 2s/div 20mv/div i out = 10a i out = 0a 20mv/div 20mv/div 2s/div 20mv/div v in = 12v v out = 1.8v f sw = 615khz i out = 10a i out = 5a i out = 0a v in = 12v v out = 2.5v f sw = 615khz 20mv/div 20mv/div 2s/div 20mv/div i out = 10a i out = 5a i out = 0a v in = 12v v out = 3.3v f sw = 800khz 20mv/div 20mv/div 2s/div 20mv/div i out = 10a i out = 5a i out = 0a -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 012345678910 time (ms) v out (v) v out = 1.2v t fall = 5ms v in = 12v -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 012345678910 time (ms) v out (v) v out = 1.2v t rise = 5ms v in = 12v
zl9010m 12 fn8422.2 january 22, 2015 submit document feedback derating curves operating conditions: t a = +25c, no air flow. f sw corresponds to those used in efficiency curves. c out = 3 x 100f + 1 x 330f. typical values are used unless otherwise noted. figure 15. derating curve, 5v in for various output voltages, no air flow figure 16. derating curve, 12v in for various output voltages, no air flow figure 17. power loss curve, 5v in for various output voltages figure 18. power loss curve, 12v in for various output voltages 0 5 6 7 8 9 10 60 70 80 90 100 110 130 ambient temperature (c) i out (a) 120 4 3 2 1 5v in _1v out 5v in _3.3v out 0 5 6 7 8 9 10 60 70 80 90 100 110 130 ambient temperature (c) i out (a) 120 4 3 2 1 12v in _1v out 12v in _1.8v out 12v in _3.3v out 0.0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 7 8 9 10 loss (w) i out (a) 1.0v 400khz 3.3v 471khz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 1 2 3 4 5 6 7 8 9 10 loss (w) i out (a) 1.8v 615khz 3.3v 800khz 1.0v 400khz
zl9010m 13 fn8422.2 january 22, 2015 submit document feedback figure 19. test circuit for all performance and derating curves notes: 21. the pmbus requires pull-up resistors. please refer to the pmbus specifications for more details. 22. the ddc bus requires a pull-up resistor. the resistance will va ry based on the capacitive loading of the bus (and on the num ber of devices connected). the 10k default value, assuming a maximum of 100pf per device, provides the necessary 1s pull-up rise time. please refer to ? digital-dc bus ? on page 23 for more details. 23. additional capacitance may be required to meet specific transient response targets. salrt sda scl ddc en c5 100f ferrite bead blm15bd102sn1d, or 2.2 c2 22f c3 330f (optional) zl9010m vdd.a8 a8 vdd.a7 a7 xtemp a6 ddc a5 en a4 pg a3 v25.a2 a2 sgnd.c1 c1 dgnd d1 v25.a1 a1 sa f1 vin pad1 sw pad4 vout pad5 sync e1 scl g1 sgnd.pad3 pad3 pgnd.pad2 pad2 sda h1 salrt j1 fc0 k1 v1.l1 l1 v1.l2 l2 ss l3 vtrk l4 fb+ l6 fb- l7 isenb l8 vr h9 pgnd.f10 f10 v25.b3 b3 v25.b6 b6 c1 22f rset c7 330f c6 100f rsa c4 100f sgnd sgnd vin sgnd sgnd gnd vout gnd ( note 21 ) ( n o t e 2 2 ) pmbus (see ta b l e 3 for rsa value) (see ta b l e 4 for rset value) ( note 23 )
zl9010m 14 fn8422.2 january 22, 2015 submit document feedback application information internal bias and input voltage considerations beside vin supplying the main power conversion, the zl9010m employs two internal low dropout (ldo) regulators to supply bias voltages for internal circuitry allo wing it to operate from a single input supply. the internal bias regulators are as indicated in the following: vr - the vr ldo provides a regulated 5v bias supply for the mosfet driver circuits. it is powered from the vdd pin. v25 - the v25 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from an internal 5v node. when the input supply (vdd) is higher than 5.5v, the vr pin should not be connected to any other pin. due to the dropout voltage associated with the vr bias regula tor, the vdd pin can be connected to the vr pin for designs operating from a supply below 5.5v. the internal bias regulators are no t designed to be outputs for powering other circuitry, so keep current into the vdd pin below 80ma. typically, vdd is connected directly to vin. in the case that vdd is powered separately from vin, the recommended power sequence is to keep en low, power vdd and then vin. when the voltage is applied to vin, vdd should also be applied to avoid unintentional turn-on of the intern al high-side mosfet. if the vdd voltage is different from vin, prebias start-up and auto-compensation may not work correctly as the vdd voltage is used to measure input voltage as part of the prebias and auto-compensation calculation. design trade-offs with switching frequency for design of the buck power st age, there is a trade-off when choosing switching frequency to achieve higher power supply efficiency, output ripple and transient response. for output voltages below 2v, a lower switching frequency results in higher efficiency. a lower output ripple and faster transient response is achieved with higher switching frequencies and thereby can reduce the required amount of output capacitance. also, given an input to output voltage relation, there is a limitation on the allowable switching frequency due to normal part operation. see ? switching frequency and pll ? on page 18 for more considerations. to start the design with a goal of high efficiency, select a frequency based on table 1 . to achieve good transient response, a minimum switching frequency of 615khz is recommended. completing a power supply design to achieve a power supply design with digital capabilities using zl9010m, only input and output ca pacitors and two resistors are needed. the two resistors are instal led on the sa and v1 pins for setting the pmbus address and ou tput voltage, respectively. selection of the input capacitor the input filter capacitor should be based on how much ripple the supply can tolerate on the dc input line. the larger the capacitor, the less ripple expected, but consideration should be taken for the higher surge current during power-up. the zl9010m provides the soft-start function that controls and limits the current surge. the value of the input capacitor can be calculated by equation 1 : where: c in(min) is the minimum input capacitance (f) required i o is the output current (a) d is the duty cycle (v o /v in ) v p-p(max) is the maximum peak-to-peak voltage (v) f sw is the switching frequency (hz) in addition to the bulk capacita nce, some low equivalent series resistance (esr) ceramic capacitance should be placed as close as possible to decouple between the drain terminal of the high-side mosfet (vin pad1) and the source terminal of the low-side mosfet (pgnd pad2). this is used to reduce voltage ringing created by the switching current across parasitic circuit elements. this ripple?s (i cinrms ) impact should be considered and can be determined from equation 2 : without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated in equation 2 to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. selection of the output capacitors the zl9010m is designed for low output voltage ripple. the output voltage ripple an d transient requirements can be met with bulk output capacitors (c out) with low esr; the recommended minimum esr is <6m . c out can be a low esr tantalum capacitor, a low esr polymer capacitor or a ceramic capacitor. the typical output capacitance range is from 200f to 1200f and decoupling ceramic output capacitors are used per phase. the optimized ou tput capacitance is 700f with an esr of 5m . the maximum recommended produc t of output capacitance and equivalent esr value is given by [c out x esr] <3600 (f x m ). with a step load faster than 0.2a/s, the recommended amount of output capacitor is 100f per ampere of step load. additional output filtering may be needed if further reduction of output ripple or dynamic transient spikes are required. table 1. optimal switching frequency for efficiency v 0 -v in 3.3v (khz) 5v (khz) 12v (khz) 0.6 - 1.5 300 400 400 1.5 - 2.5 300 615 615 2.5 - 3.6 300 400 800 c in min ?? i o d1d C ?? ? v p-p max ?? f sw ? ---------------------------------------------- - ? = (eq. 1) (eq. 2) i cinrms i out d1d C ?? ? ? =
zl9010m 15 fn8422.2 january 22, 2015 submit document feedback functional description multi-mode pins in order to simplify circui t design, the zl9010m family incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device without programming. most power management features can be configured using these pins. the multi-mode pins can respond to two types of configurations summarized in table 2 . these pins are sampled when power is applied or by issuing a pmbus command restore_factory_all. refer to ? pmbus command summary ? on page 28 . pin-strap settings: with pin strapping, parameters can be set by strapping the pins in one of three possible states: low, open, or high. these pins can be connected to sgnd for logic low as this pin provides a voltage lower than 0.8v. for logic open, they have no connection. these pins can be connected to the v25 pin for logic high settings as this pin provides a regulated voltage higher than 2v when power is applied to the vdd pin. resistor settings: allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used and only every fourth standard resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. there are five multi-mode pins in zl9010m: fc0, sa, sync, ss and v1. the multi-mode pin configuration can set zl9010m power management features and mode of operation to both single-phase and current-sharin g without any programming. sa and v1 are the only two pins that must be set for a general single-phase operation, which use the default settings associated with the other three pins, or over riding other parameters via the pmbus. the sa sets the pmbus address, phase spreading and reference/member assignment in current sharing mode. the effective phase spreading depends on the mode of operation. the reference/member is pre-assigned in current sharing mode and up to 8 two-phase with 5 thre e-phase current-shared group is possible. the fc0 is used to distinguish between the two modes of operation and is used in combinat ion with sa in current sharing mode. fc0 pin strapping and resistor programming in the range of 10k to 42.2k set the operation to single-phase mode, while the range of 46.4k to 178k is for current sharing mode. the fc0 also sets the autocomp and sync configuration. the sync sets the switching frequency and is only effective in single-phase mode, as sync pi ns are connected together in current-sharing mode. the ss sets the ramp timing, uvlo and tracking. the v1 sets the output voltage. the ss and v1 are the same purpose in single-phase and cu rrent-share modes. pmbus communications the zl9010m provides an pmbus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. the zl9010m can be used with any pmbus host device. in addition, the module is compatible with pmbus version 2.0 and includes a salrt line to help mitigate bandwidth limitations related to continuous fault monitoring. pull-up resistors ar e required on the pmbus as specified in the pmbus 2.0 specification. the zl9010m accepts most standard pmbus commands. when controlling the device with pmbus commands, it is re commended that the enable pin be tied to sgnd. the pmbus device address an d vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the p mbus. the device address is set using the sa pin. vout_max is determined as 10% greater than the voltage set by the v1 pin. the zl9010m supports 100khz and 400khz pmbus clock speed with communication interval of 20ms between store and restore commands and ~2ms for other general commands. pmbus module address selection each module must have its own unique serial address to distinguish between other devices on the bus. the module address is set by connecting a resistor between the sa pin and sgnd. table 3 lists the available module addresses. table 2. multi-mode pin configuration pin tied to value low (logic low) <0.8vdc open (n/c) no connection high (logic high) >2.0vdc resistor to sgnd set by resistor value table 3. pmbus address values r sa (k )pmbus address low 0x23 open 0x24 high 0x25 10 0x50 11 0x51 12.1 0x52 13.3 0x53 14.7 0x54 16.2 0x55 17.8 0x56 19.6 0x57 21.5 0x58 23.7 0x59 26.1 0x5a 28.7 0x5b 31.6 0x5c
zl9010m 16 fn8422.2 january 22, 2015 submit document feedback phase spreading for a single-phase mode of operation when multiple point-of-load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. to enable spreading, all converters must be synchronized to the same switching clock. the fc0 pin is used to set the configuration of the sync pin fo r each device as described in ? switching frequency and pll ? on page 18 . selecting the phase offset for the device in a standalone mode of operation is accomplished by selecting a device address according to the equation 3 : for example: ? a device address of 0x50 or 0x60 would configure no phase offset ? a device address of 0x51 or 0x61 would configure 45 of phase offset ? a device address of 0x52 or 0x62 would configure 90 of phase offset the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the pmbus interface. refer to ? pmbus command summary ? on page 28 for further details. output voltag e selection the output voltage may be set to a voltage between 0.6v and 3.6v provided that the input volt age is higher th an the desired output voltage by an amount su fficient to prevent the device from exceeding its maximum duty cycle specification. the v1 pins are used to set the output voltage using a single resistor, r set between the v1 pins and sgnd. table 4 lists the available output voltage setti ngs with a single resistor. 34.8 0x5d 38.3 0x5e 42.2 0x5f 46.4 0x60 51.1 0x61 56.2 0x62 61.9 0x63 68.1 0x64 75 0x65 82.5 0x66 90.9 0x67 100 0x68 110 0x69 121 0x6a 133 0x6b 147 0x6c 162 0x6d 178 0x6e table 3. pmbus address values (continued) r sa (k )pmbus address (eq. 3) phase offset device address 45 ? ? = )v out low 1.20 open 1.50 high 3.30 10 0.60 11 0.65 12.1 0.70 13.3 0.75 14.7 0.80 16.2 0.85 17.8 0.90 19.6 0.95 21.5 1.00 23.7 1.05 26.1 1.10 28.7 1.15 31.6 1.20 34.8 1.25 38.3 1.30 42.2 1.40 46.4 1.50 51.1 1.60 56.2 1.70 61.9 1.80 68.1 1.90 75 2.00 82.5 2.10 90.9 2.20 100 2.30 110 2.50
zl9010m 17 fn8422.2 january 22, 2015 submit document feedback the output voltage may also be set to any value between 0.6v and 3.6v using a pmbus command over the pmbus interface. refer to ? pmbus command summary ? on page 28 . the r set resistors program places an upper limit in output voltage setting through pmbus programming to 10% above the value set by the resistors. start-up procedure the zl9010m follows a specific internal start-up procedure after power is applied to the vdd pin. table 5 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable pr ior to asserting the en pin. the device requires approximately 5ms to 6ms to check for specific values stored in its internal memory. if the user has stored values in memory, those values will be loaded. the device will then check the status of all multi-mode pins and load the values associated with the pin settings. once this process is completed, the device is ready to accept commands via the pmbus interface and the device is ready to be enabled. once enabled, the device requires a minimum delay period following an enable signal and prior to ramping its output, as described in ? soft-start delay and ramp times ? on page 17 . if a soft-start delay period le ss than the minimum has been configured (using pmbus commands ), the device will default to the minimum delay period. if a delay period greater than the minimum is configured, the device will wait for the configured delay period prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the preconfigured soft-start ramp time that has been set using the ss pin. it should be noted that if the en pin is ti ed to vdd, the device will still require approximately 5ms to 6m s before the output can begin its ramp-up as described in table 5 . soft-start delay and ramp times it may be necessary to set a delay when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current manageme nt strategy or to precisely control how fast a load ic is turned on. the zl9010m gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start ramp timer enables a precisely controlled ramp to the nominal v out value that begins once the delay period has expired. the ramp-up is guaranteed monotonic and its slope may be precisely set using the ss pin. the soft-start delay and ramp times can be set to a custom value by pin-strapping or connecting a re sistor from the ss pin to sgnd using the appropriate resistor value from table 6 . see ? input undervoltage lockout ? on page 20 for further explanation of uvlo setting using ss pin. the value of this resistor is measured upon start-up or restore and will not change if the resistor is varied after power has been applied to the zl9010m. 121 2.80 133 3.00 147 3.30 162 3.60 table 4. single resistor v out setting (continued) r set (k )v out table 5. zl9010m start-up sequence step # step name description time duration 1 power applied input voltage is applied to the zl9010m?s vdd pin. depends on input supply ramp time 2 internal memory check the device will check for va lues stored in its internal memory. this step is also performed after a restore command. approximately 5ms to 6ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads valu es configured by the multi-mode pins. 4 device ready the device is ready to accept an enable signal. 5 pre-ramp delay the device requires a minimum delay period following an enable signal and prior to ramping its output, as described in ? soft-start delay and ramp times ? on page 17 . table 6. soft-start pin-st rap/resistor settings r ss (k ) delay time (ms) ramp time (ms) uvlo (v) low 5 2 4.5 open 5 5 high 10 10 10 5 2 3 11 5 5 12.1 10 13.3 20 14.7 5 10 16.2 10 17.8 20
zl9010m 18 fn8422.2 january 22, 2015 submit document feedback with the ss pin open, the defaul t value for delay time and ramp time is 5ms. the soft-start delay and ramp times are set to custom values via the pmbus interface. when the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). when the soft-start ramp period is set to 0ms, the ou tput ramps up as quickly as the output load capacitance and loop settings allow. it is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current. the zl9010m has a minimum t on_delay requirement that is a function of the operating mode. table 7 shows the different mode configurations and the minimum t on_delay required for each mode. current sharing is configured with the ishare_config pmbus command, auto compensation is configured with the auto_comp_config command and standby mode is configured as low power with the user_config command. refer to ? pmbus command summary ? on page 28 . resistor programming on the ss pi n with a delay time of 20ms can be used to satisfy the minimum t on_delay of 15ms. power-good the zl9010m provides a power-good (pg) signal that indicates the output voltage is within a sp ecified tolerance of its target level and no fault condition exists . by default, the pg pin asserts if the output is within +15/-10% of the target voltage. these limits and the polarity of the pin may be changed via the pmbus interface. refer to ? pmbus command summary ? on page 28 . a pg delay period is defined as the time when all conditions within the zl9010m for asserting pg are met, to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the zl9010m pg delay is set to 1ms and may be changed using the pmbus as described in ? pmbus command summary ? on page 28 . by default, the zl9010m pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 6ms, the pg delay is set to 6ms. the pg delay may be set independently of the soft-start ramp using the pmbus as described in ? pmbus command summary ? on page 28 . if auto comp is enabled, the pg timing is further controlled by the pg assert parameter, as described in ? loop compensation ? on page 19 . switching frequency and pll the zl9010m incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other intersil digital devices. with the fc0 pin, the sync pin can be configured as input, auto detect and output. pinstrap resistor setting to ?i nput? mode is applicable for member devices used in current sharing mode only. when multiple modules are used together, connecting the sync pins together will force all devices to synchronize with each other. one device must set its sync pin as an output and the remaining devices must have their sync pins set as auto detect. sync auto detect in auto detect mode, the module will check for a clock signal on the sync pin immediately after power-up. in this case, the incoming clock signal must be in the range of 300khz to 1.0mhz and must be stable within 10s after v25 rises above 2.25v. if the device is in low power mode, it will check for a clock signal on the sync pin immediately after en goes true. in this case, the incoming clock signal must be in range and stable before en goes true. if a clock signal is present, the zl9010m's oscillator will then synchronize with the rising edge of the external clock. if no incoming clock signal is present, the zl9010m will configure the switching frequency according to an external resistor, r sync , connected between sync and sgnd using table 8 , given that fc0 used pin-strap or has a resistor r fc0 in the range of 10k to 13.3k . when fc0 is open, or used with resistor settings in the range, the switching frequency of the zl9010m is set to a default of 615khz. the module will only read the sync pin connection during the first start- up sequence; changes to sync pin connections will not affect f sw until the power (v dd ) is cycled 19.6 5 2 4.5 21.5 10 23.7 5 5 26.1 10 28.7 20 31.6 5 10 34.8 10 38.3 20 42.2 5 2 10.8 46.4 10 51.1 5 5 56.2 10 61.9 20 68.1 5 10 75 10 82.5 20 table 7. minimum t on_delay vs operating mode current sharing autocomp low-power standby min. t on_delay (ms) x disabled false 5 disabled enabled false 5 disabled x true 10 enabled disabled true 15 enabled enabled x 15 table 6. soft-start pin-strap/resistor settings (continued) r ss (k ) delay time (ms) ramp time (ms) uvlo (v)
zl9010m 19 fn8422.2 january 22, 2015 submit document feedback off and on. frequency modifications without restarting the v dd power can disable the sync auto detect function. sync output when the sync pin is configured as an output via pmbus, the device will run from its internal oscillator and will drive the resulting internal oscillator signal onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. when fc0 is used with resistor settings in the range of 14.7k to 31.6k , the zl9010m drives the sync pin with frequency as described in table 9 and will ignore any resistor settings on sync pin. similarly, when fc0 is used with selected value of resistors in the range of 46.4k to 178k , the zl9010m operates in current sharing mode with the sync pin providing clock out. when fc0 is used with resistor settings in the range of 34.8k to 42.2k , the zl9010m will first read the sync pin connection and drives the sync pi n with the frequency described in table 8 . in this mode, the sync pin should not be pin strapped to low or high (voltage source). it is recommended to connect a buffer with high impedance, as seen by the sync pin of the module providing the clock out, to subsequently drive the sync pin of other devices. sync setting via pmbus consideration the switching frequency can be set to any value between 300khz and 1.0mhz using the pmbus interface. the available frequencies below 1.0mhz are defined by f sw = 8mhz/n, where the whole number n is 8 ? n ?? 27. refer to ? pmbus command summary ? on page 28 . if a value other than f sw = 8mhz/n is entered using a pmbus command, the internal circuitry will select the valid switching frequency value that is closest to the entered value. for example, if 810khz is entered, the device will select 800khz (n = 10). loop compensation the zl9010m operates as a voltage-mode synchronous buck controller with a fixed frequency pwm scheme. the module is internally compensated via the pmbus interface. the auto compensation feature measures th e characteristics of the power train and calculates the proper tap coefficients and can be configured according to an external resistor, r fc0 , connected between fc0 and sgnd in table 9 . if the device is configured to store auto comp values, the calculated compensation values will be saved in the auto comp store and may be read back through the pid_taps command. if repeat mode is enabled, the first auto comp results after the first ramp will be stored; the values calculated periodically are not stored in the auto comp store. when compensation values are saved in the auto comp store, the device will use those compensation values on subsequent ramps. in repeat mode, the latest auto comp results will alwa ys be used during operation. stored auto comp results can only be cleared by disabling auto comp store, which is not permitted while the output is enabled. however, sending the autocomp_control command while enabled in store mode will cause the next results to be stored, overwriting previously stored values. if auto compensation is disabled, the device will use the compensation parameters that are stored in the default_store or user_store. if the pg assert parameter is set to ?use pg delay,? pg will be asserted according to the power_good_delay command, after which auto comp will begin. when auto comp is enabled, the user must not program a power-good delay that will expire before the ramp is finished. if pg assert is set to ?after auto comp," pg will be asserted im mediately after the first auto comp cycle completes (power_good_delay will be ignored). table 8. switching frequency pin-strap/resistor settings sync pin/ r sync (k ) f sw (khz) sync pin/ r sync (k ) f sw (khz) low 400 23.7 471 open 615 26.1 533 high 800 28.7 571 14.7 296 31.6 615 16.2 320 34.8 727 17.8 364 38.3 800 19.6 400 46.4 889 21.5 421 51.1 1000 table 9. fc0 pin-strap/resistor settings fc0 pin/ r fc0 (k ) autocomp config sync pin config sync override ac single/ disable ac gain store values low auto comp disabled auto detect open single 70 not stored high store in flash 10 single 50 not stored auto detect 11 store in flash 12.1 90 not stored 13.3 store in flash 14.7 auto comp disabled output 400khz 16.2 single 70 not stored 17.8 store in flash 19.6 auto comp disabled 615khz 21.5 single 70 not stored 23.7 store in flash 26.1 auto comp disabled 800khz 28.7 single 70 not stored 31.6 store in flash 34.8 auto comp disabled depend on rsync 38.3 single 70 not stored 42.2 store in flash
zl9010m 20 fn8422.2 january 22, 2015 submit document feedback the routine can be set via the pmbus interface to execute one time after ramp or periodically while regulating and have either pg assert behavior described earlier. note that the auto compensation feature requires a minimum t on_delay as described in ? soft-start delay and ramp times ? on page 17 . the auto comp gain control scales the auto comp results to allow a trade-off between transi ent response and steady-state duty cycle jitter. a setting of 100% will provide the fastest transient response while a setting of 10% will produce the lowest jitter. with resistor settings, auto co mpensation can only be set to execute one time after ramp with option to store auto comp values. with auto compensation disabled, pg is asserted according to power_good_delay. with auto compensation executed once and auto comp values not stored, pg is asserted after auto compensation is complete at every start-up event. with auto compensation executed once and auto comp values stored, pg is asserted after auto compensation is complete at the first start-up event and is asserted according to power_good_delay for subsequent start-up event along with using the stored auto comp values from the first start-up. by default with fc0 open, auto co mpensation is configured to execute one time after ramp with 70% auto comp gain, pg asserted immediately after the first auto comp cycle completes and auto comp values not stored. note that if auto comp is enabled, for best results v in must be stable before auto comp begins, as shown in equation 4 . the auto compensation function can also be configured via the auto_comp_config command and controlled using the auto_comp_control command over the pmbus interface. please refer to ? pmbus command summary ? on page 28 for further details. adaptive diode emulation adaptive diode emulation mode turns off the low-side fet gate drive at low load currents to prevent the inductor current from going negative, reducing the ener gy losses and increasing overall efficiency. diode emulation is available to single-phase devices only. note: the overall bandwidth of the device may be reduced when in diode emulation mode. disablin g the diode emulation prior to applying significant load steps is recommended. input undervoltage lockout the input undervoltage lockout (uvlo) prevents the zl9010m from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 2.85v and 16v using the pmbus interface. once an input undervoltage faul t condition occurs, the device can respond in a number of ways, as follows: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device remains in shutdown until instructed to restart. 3. initiate an immediate shutdown until the fault is cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the module. the cont roller continuously checks for the presence of the fault condition. if the fault condition is no longer present, the zl9010m is re-enabled. output overvoltage protection the zl9010m offers an internal output overvoltage protection circuit that can be used to prot ect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the fb+ pin) to a threshold set to 15% higher than the target output voltage (the default setting). if the fb+ voltage exceeds this threshold, the pg pin deasserts and the controller can then respond in a number of ways, as follows: 1. initiate an immediate shutdown until the fault is cleared. the user can select a specific number of retry attempts. 2. turn off the high-side and the low-side mosfets until the device attempts a restart. the default response from an over voltage fault is to immediately shut down. the controller continuously checks for the presence of the fault condition and when the fault condition no longer exists, the device is re-enabled. for continuous overvoltage protec tion when operating from an external clock, the only allowed response is an immediate shutdown. please refer to ? pmbus command summary ? on page 28 for details on how to select specif ic overvoltage fault response options via pmbus. output prebias protection an output prebias condition exis ts when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to sink current during start-up if a prebias condition exists at the output. the zl9010m provides prebias protection by sampling the output voltage prior to initiating an output ramp. if a prebias voltage lower than the target voltage exists after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the preconfigured ramp rate. the actual time the output takes to ramp from the prebias voltage to the target voltage varies, depending on the prebias voltage, but the total time elapsed from when the delay period expires and when the output reaches its target value, will match the preconfigured ramp time (see figure 20 ). if a prebias voltage higher than th e target voltage exists after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage and both drivers are ? v in vin nom ---------------------- - in% ?? 100% 1 256 v out ? vin nom ------------------------------- + ----------------------------------------- ? (eq. 4)
zl9010m 21 fn8422.2 january 22, 2015 submit document feedback enabled with a pwm duty cycle that would ideally create the pre-bias voltage. once the preconfigured soft-start ramp period has expired, the pg pin is asserted (assuming the prebias voltage is not higher than the overvoltage limit). the pwm then adjusts its duty cycle to match the original target vo ltage and the output ramps down to the preconfigured output voltage. if a prebias voltage higher than the overvoltage limit exists, the device does not initiate a turn-on sequence and declares an overvoltage fault condition to exist. in this case, the device responds based on the output overvoltage fault response method that has been selected. see ? output overvoltage protection ? on page 20 for response options due to an overvoltage condition. note that prebias protection is not offered for current sharing groups that also have tracking enabled. the v dd must be the same voltage as v in for proper prebias star t-up in single module operation. output overcurrent protection the zl9010m can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. the following ov ercurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an ov ercurrent fault is an immediate shutdown of the controller. the co ntroller continuously checks for the presence of the fault condition and if the fault condition no longer exists, the device is reenabled. please refer to ? pmbus command summary ? on page 28 for details on how to select specif ic overcurrent fault response options via pmbus. thermal overload protection the zl9010m includes a thermal sensor that continuously measures the internal temperat ure of the module and shuts down the controller when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but the user may set the limit to a different value if desired. see ? pmbus command summary ? on page 28 for details. note that setting a higher thermal limit via the pmbus interface may result in permanent damage to the controller. once the module has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the mo dule to restart, the controller waits the preset delay period (if configured to do so) and then checks the module temperature. if the temperature has dropped below a threshold that is appr oximately +15c lower than the selected temperature fault limit, the controller attempts to restart. if the temperature still exceeds the fault limit, the controller waits the preset delay period and retries again. the default response from a temp erature fault is an immediate shutdown of the module. the cont roller continuously checks for the fault condition and once the fault has cleared, the zl9010m is reenabled. refer to ? pmbus command summary ? on page 28 for details on how to select specific temperature fault response options via pmbus. figure 20. output responses to prebias voltages
zl9010m 22 fn8422.2 january 22, 2015 submit document feedback voltage tracking numerous high performance sy stems place stringent demands on the order in which the power supply voltages are turned on. this is particularly true when powering fpgas, asics and other advanced processor devices that require multiple supply voltages to power a single die. in most ca ses, the i/o interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications. voltage tracking protects these sensitive ics by limiting the differential voltage between multiple power supplies during the power-up and power-down sequence. the zl9010m integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin with no external components required . the vtrk pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation. figure 21 illustrates the typical connection of two tracking modules. the zl9010m offers two modes of tracking as follows and can be configured according to an external resistor, r ss , connected between ss and sgnd in table 10 or via pmbus. the t on_delay time is set to 5ms and t off_delay time is set to 35ms. the ramp time is set to 2ms, but ca n track to a slower ramp time, i.e., >2ms. 1. coincident . this mode configures the module to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. two options are available for this mode: - track at 100% v out limited. member rail tracks the reference rail and stops when the member reaches its target voltage figure 22 (a) . - track at 100% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin figure 22 (b) . 2. ratiometric . this mode configures the module to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor string may be used to configure a different tracking ratio: -track at 50% v out limited. member rail tracks the reference rail and stops when the member reaches 50% of the target voltage figure 23 (a) . - track at 50% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin until the member rail reaches 50% of the reference rail voltage, or if the member is configured to less than 50% of the reference the member will achieve its configured target figure 23 (b) . table 10. tracking resistor settings r ss (k ) track ratio (%) upper track limit ramp-up/down behavior 90.9 100 limited by target output does not decrease before pg 100 output always follows vtrk 110 limited by vtrk output does not decrease before pg 121 output always follows vtrk 133 50 limited by target output does not decrease before pg 147 output always follows vtrk 162 limited by vtrk output does not decrease before pg 178 output always follows vtrk figure 21. pmbus trac king configuration zl zl vout vtrk c out r sda scl sda scl c out m reference member vout_r vout_m figure 22. coincident tracking track @ 100% vout limited vref > vmem en 0 0 en ~ ~ ~ ~ toff dly ton d ly vmem vr ef track @ 100% vtrk limited vref = vmem ~ ~ toff dly ton dly vref vmem coi nci dent tracki ng vref =1.8 v vmem=0. 9v vref =1.8 v vmem=1.8v a. b. figure 23. ratiometric tracking 0 en en 0 track @ 50% vout li m ited vref = 1.8v vm em = 0. 9v ~ ~ ~ ~ toff dl y ton d ly vmem vr ef track @ 50% vtrk li m ited vref = 1.8v vm em = 0.9v rat io metri c trac ki ng vref =1.8v vmem=0. 9v ~ ~ ~ ~ ton d ly toff dl y vref vmem vref =1.8v vmem=0. 9v a. b.
zl9010m 23 fn8422.2 january 22, 2015 submit document feedback the master module device in a tracking group is defined as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is not configured for tracking mode. a delay of at least 6ms must be configured into the master device and the user may also configure a specific ramp rate. any device that is configured for tracking mode will ignore its soft-start delay and its output will take on the turn-o n/turn-off characteristics of the reference voltage present at the vtrk pin. all of the enable pins in the tracking group must be connected together and driven by a single logic source. tracking is configured via the pmbus interface by using the track_config pmbus command. refer to ? pmbus command summary ? on page 28 for further details on configuring tracking mode using pmbus. when the zl9010m is configured to the voltage tracking mode, the voltage applied to the vtrk pin acts as a reference for the member device(s) output re gulation. when the auto compensation algorithm is used the soft-start values (rise/fall times) are used to calculate the loop gain used during the turn-on/turn-off ramps. if current sharing is used, constrain the rise/fall time between 5ms and 20 ms to ensure current sharing while ramping. tracking groups in a tracking group, the device configured to the highest voltage within the group is defined as the reference device. the device(s) that track the reference is ca lled member device(s). the reference device will control the ramp delay and ramp rate of all tracking devices and is not plac ed in the tracking mode. the reference device is configured to the highest output voltage for the group and all other device(s)? output voltages are meant to track and never exceed the reference device output voltage. the reference device must be co nfigured to have a minimum ton_delay and ton-rise as shown in equation 5 : this delay allows the member device(s) to prepare their control loops for tracking following the assertion of enable. the member device toff_delay has been redefined to describe the time that the vtrk pin will follow the reference voltage after enable is de-asserted. the delay setting sets the timeout for the member's output voltage to turn off in the event that the reference output voltage does not achieve zero volts. the member device(s) must have a minimum toff_delay of as shown in equation 6 : all of the enable pins must be connected together and driven by a single logic source or a p mbus broadcast enable command may be used. the configuration settings for figures 22 and 23 are shown in tables 11 through 14 . in each case the reference and member rise times are set to the same value. voltage margining the zl9010m offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn command is set through the pmbus interface. the module?s output will be forced higher than its nominal set point when the mgn command is set high and the output will be forced lower than its nominal set point when the mgn command is set low. default margin limits of v nom 5% are pre-loaded in the factory, but the margin limi ts can be modified through the pmbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage set point determined by the v1 pin. the margin limits and the mg n command can both be set individually through the pmbus interface. additionally, the transition rate between the nomi nal output voltage and either margin limit can be configured through the pmbus interface. refer to ? pmbus command summary ? on page 28 for further instructions on modifying the margining configurations. digital-dc bus the digital-dc communications (ddc) bus is used to communicate between intersil digital modules and devices. this dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading and current sharing. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bus in order to guarantee the rise time as shown in equation 7 : t on_dly (ref) > t on_dly (mem) + t on_rise (ref) + 5ms > t on_dly (mem) + 6ms (eq. 5) t off_dly (mem) > t off_dly (ref) + t off_fall (ref) + 5ms (eq. 6) table 11. tracking configuration ( figure 22 (a) ) rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 0.9 5 5 15 5 100% v out limited table 12. tracking configuration ( figure 22 (b) ) rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 1.8 5 5 15 5 100% v trk limited table 13. tracking configuration ( figure 23 (a) ) rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 0.9 5 5 15 5 50% v out limited table 14. tracking configuration ( figure 23 (b) ) rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 1.8 5 5 15 5 50% v trk limited rise time r pu ? c load 1 ? s ? = (eq. 7)
zl9010m 24 fn8422.2 january 22, 2015 submit document feedback where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to an external 3.3v or 5v supply as long as this voltage is present prior to or during device power-up. as a rule of thumb, each device connected to the ddc bus presents approximately 10pf of capacitive loading and each inch of fr4 pcb trace introduces approximately 2pf. the ideal design uses a central pull-up resistor that is well matched to the total load capa citance. the minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that ensures a logic 0 (typically 0.8v at the device monitoring point), given the pull-up voltage and the pull-down current capability of the zl9010m (nominally 4ma). output sequencing a group of digital-dc modules or devices may be configured to power-up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas and asics that require one supply to reac h its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up. multi-device sequencing can be achieved by configuring each device through the pmbus interface. multiple device sequencing is configured by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that follows in the sequencing chain. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven lo w to initiate a sequenced turnoff of the group. refer to ? pmbus command summary ? on page 28 for details on sequencing via the pmbus interface. fault spreading digital dc modules and devices ca n be configured to broadcast a fault event over the ddc bus to the other devices in the group. when a non-destructive fault occurs and the device is configured to shut down on a fault, the device shuts down and broadcasts the fault event over the ddc bus. the other devices on the ddc bus shut down together, if config ured to do so and attempt to restart in their prescribed order, if configured to do so. active current sharing paralleling multiple zl9101m modules can be used to increase the output current capability of a single power rail. by connecting the ddc pins of each module together and configuring the modules as a current sharing rail, the units share the current equally within a few percent. figure 24 illustrates a typical connection for two modules. the zl9101m uses a low-bandwidth, first-order digital current sharing technique to balance the unequal module output loading by aligning the load lines of member modules to a reference module. droop resistance is used to add ar tificial resistance in the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and pcb layout. upon system start-up, the module with the lowest member position as selected in ishare_config is defined as the reference module. the remaining modules are members. the reference module broadcasts its current over the ddc bus. the members use the reference current information to trim their voltages (v member ) to balance the current loading of each module in the system. figure 25 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage, which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by equation 8 : where r is the value of the droop resistance. the ishare_config command is us ed to configure the module for active current sharing. the default setting is a stand-alone non-current sharing module. a curren t sharing rail can be part of a system sequencing group. for fault configuration, the curren t share rail is configured in a quasi-redundant mode. in this mode, when a member module fails, the remaining members continue to operate and attempt to maintain regulation. of the rema ining modules, the module with the lowest member position be comes the reference. if fault figure 24. current sharing group zl9010m v out zl9010m v in c out c in c out c in ddc ddc 3.3v to 5v -r -r v reference v member i member i reference i out v out figure 25. active current sharing (eq. 8) v member v out ri reference i member C ?? ? + =
zl9010m 25 fn8422.2 january 22, 2015 submit document feedback spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. the phase offset of (multi-phase) current sharing modules is automatically set to a value between 0 and 337.5 in 22.5 increments as in equation 9 : please refer to application note an2034 for additional details on current sharing. monitoring via pmbus a system controller can monitor a wide variety of different zl9010m system parameters through the pmbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be pulled low when any number of preconfigured fault conditions occur. the module can be monitored continuously for any number of power conversion parameters including the following: ?input voltage ?output voltage ? output current ? internal temperature ?external temperature ?switching frequency ? duty cycle the pmbus host should respond to salrt as follows: 1. zl device pulls salrt low. 2. pmbus host detects that salrt is now low, performs transmission with alert respon se address to find, which zl device is pulling salrt low. 3. pmbus host talks to the zl devi ce that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly un til all faults are cleared. refer to ? pmbus command summary ? on page 28 for details on how to monitor specific parameters via the pmbus interface. temperature monitoring using the xtemp pin the zl9010m supports measurement of an external device temperature using either a thermal diode integrated in a processor, fpga or asic, or using a discrete diode-connected 2n3904 npn transistor. figure 26 illustrates the typical connections required. snapshot parameter capture the zl9010m offers a special feature that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config command to 1. the snapshot feature enables the user to read parameters via a block read transfer through the smbus. this can be done during normal operation, although it should be noted that reading the 32 bytes occupies the smbus for a period of time. the snapshot_control command enables the user to store the snapshot parameters to flash memory in response to a pending fault, as well as to re ad the stored data from flash memory after a fault has occurred. in order to read the stored data from flash memory, two conditions must apply: 1. the module should be disabled. 2. snapshot mode should be di sabled by changing bit 1 of misc_config to 0. this is to prevent firmware from updating ram values after the fault with current values. table 15 describes the usage of snapshot_control command. automatic writes to flash memory following a fault are triggered when any fault threshold level is exceeded, provided that the specific fault's re sponse is to shut down (writing to flash memory is not allowed if the device is configured to retry following the specific fault conditions). it should be noted that the device's vdd voltage must be maintained during the time when the device is writing the data to flash memory; a process that requ ires up to 1400s. undesirable results may be observed if the device's vdd supply drops below 3.0v during the process. phase offset smbus address 4:0 ?? current C = (eq. 9) share position ? 22.5 ? figure 26. external temperature monitoring zl sgnd xtemp discrete npn 2n3904 zl sgnd xtemp embedded thermal diode p fpga dsp asic 100pf 100pf
zl9010m 26 fn8422.2 january 22, 2015 submit document feedback the following is a recommended procedure for using the snapshot parameter capture after a fault: 1. configure the module using config file (optional) 2. enable the snapshot mode by setting bit 1 of misc_config command to 1. this can be done before or after the module is enabled. note: do not store misc_config: snapshot setting in default/user store. 3. at this point the module starts capturing operational parameters in ram for snapshot, every firmware cycle. 4. the module is configured to capture operational parameters after a fault during operation. 5. after the fault, disable the snapshot mode by setting bit 1 of misc_config command to 0. this is to prevent firmware from updating ram values after the fault with current values. 6. disable the module. 7. send snapshot_control command 1 to read the stored data from flash memory into ram at any time. issue a snapshot command to read the data from ram via smbus. 8. repeat step 7 to retrieve snapshot parameters after a power cycle. it is important to make sure snapshot mode is disabled in misc_config command. nonvolatile memory and device security features the zl9010m has internal nonvolatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the module to a level that has been made available to them. during the initialization process, the zl9010m checks for stored values contained in its intern al non-volatile memory. the zl9010m offers two internal memory storage units that are accessible by the user as follows: 1. default store : the zl9010m has a default configuration that is stored in the default store in the controller. the module can be restored to its default settings by issuing a restore_default_all command over the pmbus. 2. user store : the user can modify certain power supply settings as described in this datasheet. the user stores their configuration in the user store. refer to ? pmbus command summary ? on page 28 for details on how to set specific security measures via the pmbus interface. layout guide to achieve stable operation, low losses and good thermal performance some layout considerations are necessary ( figure 27 ). ? establish a continuous ground plane connecting dgnd pin and pgnd pin f10 with via directly the ground plane. ? establish sgnd island connect ing (pad 3, pin c1) and the return path of analog signals and resistor programming pin signals. ? establish pgnd island connecting pgnd (pad 2, 5, pin f10). ? make a single point connection between sgnd and pgnd islands. ? place a high frequency ceramic capacitor between (1) vin and pgnd (pad 2) (2) vout and pgnd (pad 5) as close to the module as possible to minimize high frequency noise. high frequency ceramic capacitors close to the module between vout and pgnd will help to minimize noise at the output ripple. ? use large copper areas for power path (vin, pgnd, vout, sw) to minimize conduction loss and thermal stress. also, use multiple vias to connect the power planes in different layers. ? connect remote sensed traces fb+ and fb- to the regulation point to achieve a tight output voltage regulation and keep them in parallel. route a trace from fb- to a location near the load ground and a trace from fb+ to the point-of-load where the tight output voltage is desired. ? avoid routing any sensitive signal traces, such as the vout, fb+, fb- sensing point near the sw pad.
zl9010m 27 fn8422.2 january 22, 2015 submit document feedback thermal considerations experimental power loss curves along with ja from thermal modeling analysis can be used to evaluate the thermal consideration for the module. the derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125c. in actual application, other heat sources and design margin should be considered. package description the structure of zl9010m belongs to the high density array (hda) package. this kind of package has advantages, such as good thermal and electrical conductivity, low weight and small size. the hda package is applicable for surface mounting technology. the zl9010m contains several types of devices, including resistors, capacitors, inductors and control ics. the zl9010m is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper lead frame and multi component assembly is overmolded with polymer mold compound to protect these devices. the package outline and typical pcb layout pattern design and typical stencil pattern design are shown in the package outline drawing y32.17.2x11.45 on page 69 . the module has a small size of 17.2mmx11.45mmx2.5mm. figure 28 shows typical reflow profile parameters. these guidelines are general design rules. users could modify parameters according to their application. pcb layout pattern design the bottom of the zl9010m is a lead-frame footprint, which is attached to the pcb by surface mounting process. the pcb layout pattern is shown in the package outline drawing y32.17.2x11.45 on page 69 . the pcb layout pattern is essentially 1:1 with the hda ex posed pad and i/o termination dimensions. the thermal lands on the pcb layout should match 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about 1.0 ounce copper. although adding more vias (by decreasing vi a pitch) will improve the thermal performance, diminishing returns w ill be seen as more and more vias are added. simply use as many vias as practical for the thermal land size and your bo ard design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2mil to 3m il) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joins. stencil aperture size to land size ratio should typically be 1:1. the aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the la rger thermal lands, it is recommended that an array of sm aller apertures be used instead of one large aperture. it is reco mmended that the stencil printing area cover 50% to 80% of the pcb layout pattern. a typical solder stencil pattern is shown in the package outline drawing y32.17.2x11.45 on page 69 . the gap width pad to pad is 0.6mm. the user should consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. electropolishing ?smooths? the aperture walls resulting in reduced surface friction and better paste release which reduces voids. using a trapezoidal section aperture (tsa) also promotes paste release and forms a "brick like" paste deposit that assists in firm component placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) hda. sgnd pgnd pgnd pgnd dgnd sgnd vin sw vout vr pgnd fb+ fb- sgnd kelvin sensing lines figure 27. recommended layout
zl9010m 28 fn8422.2 january 22, 2015 submit document feedback reflow parameters due to the low mount height of the hda, "no clean" type 3 solder paste per ansi/j-std-005 is recommended. nitrogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the hda. the profile given in figure 28 is provided as a guideline, to be customized for varying manufacturing practices and applications. figure 28. typical reflow profile 0300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +150c to +200c for 60s~180s ramp rate ? 1.5c from +70c to +90c peak temperature ~+245c; typically 60s-150s above +217c keep less than 30s within 5c of peak temp. pmbus command summary command code command name description type data format default value default setting page 01h operation sets enable, disable and v out margin modes. r/w byte bit page 34 02h on_off_config configures device to enable from en pin or opeartion command. r/w byte bit 16h pin enable soft off page 35 03h clear_faults clears fault indications. send byte page 35 11h store_default_all stores all pmbus values written since last restore at default level. send byte page 35 12h restore_default_all restores pmbus settings that were stored at default level. send byte page 36 15h store_user_all stores all pmbus values written since last restore at user level. send byte page 36 16h restore_user_all restores pmbus settings that were stored in user level. send byte page 36 20h vout_mode preset to defined data format of v out commands. read byte 13h linear mode, exponent = -13 page 36 21h vout_command sets the nominal value of v out . r/w word l16u pin strap page 36 22h vout_trim sets trim value on v out . r/w word l16s 0000h 0v page 37 23h vout_cal_offset applies a fixed offset voltage to the vout_command. r/w word l16s 0000h 0v page 37 24h vout_max sets the maximum possible value of v out . r/w word l16u 1.1*vout pin strap page 37 25h vout_margin_high sets the value of the v out during a margin high. r/w word l16u 1.05*vout pin strap page 37 26h vout_margin_low sets the value of the v out during a margin low. r/w word l16u 0.95*vout pin strap page 37 27h vout_transition_rate sets the transition rate during margin or other change of v out . r/w word l11 ba00h 1v/ms page 38 28h vout_droop sets the loadline (v/i slope) resistance for the rail. r/w word l11 0000h 0mv/a page 38 32h max_duty sets the maximum allowable duty cycle. r/w word l11 ead6h 90.75% page 38 33h frequency_switch sets the switchin g frequency. r/w word l11 pin strap page 38
zl9010m 29 fn8422.2 january 22, 2015 submit document feedback 37h interleave sets a phase offset between devices sharing a sync clock. r/w word bit based on pmbus address page 39 38h iout_cal_gain sense resistance for inductor dcr current sensing. r/w word l11 c20fh 2.06m /a page 39 39h iout_cal_offset sets the current- sense offset. r/w word l11 bd4dh -1.35a page 39 40h vout_ov_fault_limit sets the v out overvoltage fault threshold. r/w word l16u 1.15*vout pin strap page 39 41h vout_ov_fault_response configures the v out overvoltage fault response. r/w byte bit 80h disable and no retry page 40 44h vout_uv_fault_limit sets the v out undervoltage fault threshold. r/w word l16u 0.8*vout pin strap page 40 45h vout_uv_fault_response configures the v out undervoltage fault response. r/w byte bit 80h disable and no retry page 41 46h iout_oc_fault_limit sets the i out average overcurrent fault threshold. r/w word l11 db00h 24a page 41 4bh iout_uc_fault_limit sets the i out average undercurrent fault threshold. r/w word l11 dd00h -24a page 41 4fh ot_fault_limit sets the over-temperature fault threshold. r/w word l11 ebe8h +125c page 41 50h ot_fault_response configures the over-temperature fault response. r/w byte bit 80h disable and no retry page 42 51h ot_warn_limit sets the over-temperature warning limit. r/w word l11 eb70h +110c page 42 52h ut_warn_limit sets the under-temperature warning limit. r/w word l11 e580h -40c page 42 53h ut_fault_limit sets the under-temperature fault threshold. r/w word l11 e490h -55c page 43 54h ut_fault_response configures the under-temperature fault response. r/w byte bit 80h disable and no retry page 43 55h vin_ov_fault_limit sets the v in overvoltage fault threshold. r/w word l11 d3a0h 14.5v page 43 56h vin_ov_fault_response configures the v in overvoltage fault response. r/w byte bit 80h disable and no retry page 44 57h vin_ov_warn_limit sets the v in overvoltage warning limit. r/w word l11 d380h 14.0v page 44 58h vin_uv_warn_limit sets the v in undervoltage warning limit. r/w word l11 ca40h 4.5v page 44 59h vin_uv_fault_limit sets the v in undervoltage fault threshold. r/w word l11 ca00h 4.0v page 44 5ah vin_uv_fault_response configures the v in undervoltage fault response. r/w byte bit 80h disable and no retry page 45 5eh power_good_on sets the voltage threshold for power-good indication. r/w word l16u 0.9*vout pin strap page 45 60h ton_delay sets the de lay time from enable to start of v out rise. r/w word l11 ca80h 5ms page 45 61h ton_rise sets the rise time of v out after enable and ton_delay. r/w word l11 ca80h 5ms page 45 64h toff_delay sets the delay time from disable to start of v out fall. r/w word l11 ca80h 5ms page 46 65h toff_fall sets the fall time for v out after disable and toff_delay. r/w word l11 ca80h 5ms page 46 pmbus command summary (continued) command code command name description type data format default value default setting page
zl9010m 30 fn8422.2 january 22, 2015 submit document feedback 78h status_byte summary of most critical faults. read byte bit 00h no faults page 46 79h status_word summary of critical faults. read word bit 0000h no faults page 47 7ah status_vout reports v out warnings/faults. read byte bit 00h no faults page 47 7bh status_iout reports i out warnings/faults. read byte bit 00h no faults page 47 7ch status_input reports input warnings /faults. read byte bit 00h no faults page 48 7dh status_temperature reports temperature warnings/faults. read byte bit 00h no faults page 49 7eh status_cml reports communication, memory, logic errors. read byte bit 00h no faults page 49 80h status_mfr_specific report s voltage monitoring/clock sync faults. read byte bit 00h no faults page 50 88h read_vin reports input voltage measurement. read word l11 page 50 8bh read_vout reports input voltage measurement. read word l16u page 50 8ch read_iout reports output current measurement. read word l11 page 50 8dh read_temperature_1 reports temperature reading internal to the device. read word l11 page 50 8eh read_temperature_2 reports temperature reading external to the device. read word l11 page 50 94h read_duty_cycle reports actual duty cycle. read word l11 page 51 95h read_frequency reports actual switching frequency. read word l11 page 51 98h pmbus_revision returns the revisi on of the pmbus. read byte hex 01h page 51 99h mfr_id sets a user defined identification. r/w block asc page 51 9ah mfr_model sets a user defined model. r/w block asc page 51 9bh mfr_revision sets a user defined revision. r/w block asc page 51 9ch mfr_location sets a user defined location identifier. r/w block asc page 52 9dh mfr_date sets a user defined date. r/w block asc page 52 9eh mfr_serial sets a user defined serialized identifier. r/w block asc page 52 b0h user_data_00 sets a user defined data. r/w block asc page 52 bch auto_comp_config configures the auto compensation features. r/w byte cus 69h auto comp enabled gain = 70% page 53 bdh auto_comp_control causes the auto comp algorithm to initiate. send byte page 53 bfh deadtime_max sets the maximum deadtime values. r/w word cus 3838h h-l = 56ns l-h = 56ns page 53 d0h mfr_config configures several manufacturer- level features. r/w word bit 6a11h refer to description page 54 d1h user_config configures several user-level features. r/w word bit 2011h refer to description page 55 d2h ishare_config configures the device for current sharing communication r/w word bit 0000h current share disabled page 56 d3h ddc_config configures the ddc bus. r/w word bit 0001h set based on pmbus address page 56 pmbus command summary (continued) command code command name description type data format default value default setting page
zl9010m 31 fn8422.2 january 22, 2015 submit document feedback d4h power_good_delay sets th e delay pg threshold and asserting the pg pin. r/w word l11 ba00h 1ms page 56 d5h pid_taps configures control loop compensator coefficients. r/w block cus calculated by autocomp page 57 d6h inductor inform the device of circuit?s inductor value r/w word l11 b200h 0.5h page 57 d7h nlr_config configure the non-linear response control parameters r/w block bit 00000000h refer to description page 58 d8h ovuv_config configures output voltage ov/uv fault detection. r/w byte bit 00h faster response, no crowbar page 58 d9h xtemp_scale scalar value that is for calibrating the external temperature r/w word l11 ba00h 1c page 58 dah xtemp_offset offset value for calibrating the external temperature r/w word l11 8000h 0c page 59 dch tempco_config sets tempco se ttings. r/w byte cus 28h 4000ppm/c with internal temp sensor correction page 59 ddh deadtime sets default deadtime settings. r/w word cus 1414h h-l = 20ns l-h = 20ns page 60 deh deadtime_config configures the adaptive deadtime optimization mode. r/w word cus 8686h adaptive deadtime disabled page 60 e0h sequence ddc rail sequencing configuration. r/w word bit 0000h prequel and sequel disabled page 61 e1h track_config configures voltage tracking modes. r/w byte bit 00h tracking disable page 61 e2h ddc_group sets rail ddc ids to obey faults and margining spreading information. r/w block bit 00000000h ignore fault spread page 61 e4h device_id returns the device identifier string. read block asc reads device version page 62 e5h mfr_iout_oc_fault_response configures the i out overcurrent fault response. r/w byte bit 80h disable and no retry page 62 e6h mfr_iout_uc_fault_response configures the i out undercurrent fault response. r/w byte bit 80h disable and no retry page 62 e7h iout_avg_oc_fault_limit sets i out average overcurrent fault threshold. r/w word l11 d3c0h 15a page 63 e8h iout_avg_uc_fault_limit sets i out average undercurrent fault threshold. r/w word l11 d440h -15a page 63 e9h misc_config sets options pertaining to advanced features. r/w word bit 2000h broadcast disabled page 63 eah snapshot returns 32-byte read-back of parametric and status values. read block bit n/a page 64 ebh blank_params indicates recently saved parameter values. read block bit ff...ffh page 64 f0h phase_control controls phase adding/dropping for current sharing configuration. r/w byte bit 00h all phases disabled page 64 f3h snapshot_control controls how snapshot values are handled. r/w byte bit page 65 pmbus command summary (continued) command code command name description type data format default value default setting page
zl9010m 32 fn8422.2 january 22, 2015 submit document feedback f4h restore_factory restores device to the factory default values. send byte page 65 fah security_level reports the security level. read byte hex 1 public security level page 65 fbh private_password sets the private password string. r/w block asc 000..00h page 67 fch public_password sets the public password string. r/w block asc 00...00h page 67 fdh unprotect identifies which commands are protected. r/w block cus ff...ffh page 67 pmbus command summary (continued) command code command name description type data format default value default setting page
zl9010m 33 fn8422.2 january 22, 2015 submit document feedback pmbus? data formats linear-11 (l11) l11 data format uses 5-bit two?s compliment exponent (n) and 11-b it two?s compliment mantissa (y) to represent real world decim al value (x). relation between real world decimal value (x), n and y is: x = y2 n linear-16 unsigned (l16u) l16u data format uses a fixed exponent (hard-coded to n = -13h) and a 16-bit unsigned integer mantissa (y) to represent real wo rld decimal value (x). relation between real world decimal value (x), n and y is: x = y2 -13 linear-16 signed (l16s) l16s data format uses a fixed exponent (hard-coded to n = -13h ) and a 16-bit two?s compliment mantissa (y) to represent real wo rld decimal value (x). relation between real world decimal value (x), n and y is: x = y2 -13 bit field (bit) break down of bit field is provided in ? pmbus command summary ? on page 28 . custom (cus) break down of custom data format is provided in ? pmbus command summary ? on page 28 . a combination of bit field and integer are common types of custom data format. ascii (asc) a variable length string of text characters uses ascii data format. data byte high data byte low exponen t ( n )mantissa ( y ) 76543210 76543210
zl9010m 34 fn8422.2 january 22, 2015 submit document feedback pmbus commands description operation (01h) definition : sets enable, disable and v out margin settings. data values of operation that force margin high or low only take effect when the mgn pin is left open (i.e ., in the nominal margin state). data length in bytes : 1 data forma t: bit type : r/w byte default value : units : n/a command operation (01h) format bit field bit position 76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value 00000000 bits 7:6 bits 5:4 bits 3:0 (not used) unit on or off margin state 00 00 0000 immediate off (no sequencing) n/a 01 00 0000 soft off (with sequencing) n/a 10 00 0000 on nominal 10 01 0000 on margin low 10 10 0000 on margin high note: bit combinations not listed above may cause command errors.
zl9010m 35 fn8422.2 january 22, 2015 submit document feedback on_off_config (02h) definition : configures the interpretation and coordination of the operation command and the enable pin (en). data length in bytes : 1 data format : bit type : r/w byte default value : 16h (device starts from enable pin with immediate off) units : n/a clear_faults (03h) definition : clears all fault bits in all registers and releases the salr t pin (if asserted) simultaneously. if a fault condition still ex ists, the bit will reassert immediately. this command will not restart a device if it has shut down, it will only clear the faults. data length in bytes : 0 data format : n/a type : send byte default valu e: n/a units : n/a reference: n/a store_default_all (11h) definition : stores, at the default level, all pmbus values that were writ ten since the last restore command. to clear the default store, perform a restore_factory then store_default_all. to add to the default store, perform a restore_default_all, write commands to be added, then store_defaul t_all. wait 20ms after a store command. data length in bytes : 0 data format : n/a type : send byte default value : n/a units: n/a command on_off_config (02h) format bit field bit position 7 access r/w function see following table bit number purpose bit value meaning 7:5 not used 000 not used 4:2 sets the default to ei ther operate any time power is present or for the on/off to be controlled by enable pin, operation command, or when both the enable pin and operation command are valid. 000 device starts any time power is pr esent regardless of enable pin or operation command states. 101 device starts from enable pin only. 110 device starts from operation command only. 111 device starts when the enable pin is active and operation ?on? command has been sent. 1 polarity of the enable pin 0 active low (pull pin low to start the device) 1 active high (pull pin high to start the device) 0 enable pin action when commanding the unit to turn off 0 use the programmed ramp down settings 1 turn off the output immediately
zl9010m 36 fn8422.2 january 22, 2015 submit document feedback restore_default_all (12h) definition : restores pmbus? settings from the nonvolatile default store memory into the operating memory. these settings are loaded at power-up if not superseded by settings in user store. security level is changed to le vel 1 following this command. th is command should not be used during device operation. data length in bytes : 0 data format : n/a type : send byte default value : n/a units: n/a store_user_all (15h) definition : stores all pmbus settings from the operating memory to the nonvolatile user store memory. to clear the user store, perform a restore_factory then store_user_all. to add to the user store, perform a restore_user_all, write commands to be added, then store_user_all. this command can be used during device operation, but the device will be unresponsive for 20ms while storing values. data length in bytes : 0 data format : n/a type : send byte default value : n/a units: n/a restore_user_all (16h) definition: restores all pmbus settings from the user store memory to the operating memory. command performed at power-up. security level is changed to level 1 following this comm and. this command can be us ed during device operation. data length in bytes: 0 data format: n/a type: send byte default value: n/a units: n/a vout_mode (20h) definition: reports the v out mode and prides the exponent used in calculating several v out settings. fixed with linear mode with default exponent (n) = -13 data length in bytes: 1 data format: bit type: read byte default value: 13h (linear mode, n = -13) units: n/a vout_command (21h) definition: this command sets or reports the target output voltage. this command cannot set a value higher than either vout_max or 110% of the pin strap v out setting. data length in bytes: 2 data format: l16u type: r/w default value: pin strap setting units: volts range: 0v to vout_max
zl9010m 37 fn8422.2 january 22, 2015 submit document feedback vout_trim (22h) definition: sets v out trim value. the two bytes are formatted as a two?s comp lement binary mantissa, used in conjunction with the exponent set in vout_mode. data length in bytes: 2 data format: l16s type: r/w word default value: 0000h (0v) units: volts range: -4v to 4v vout_cal_offset (23h) definition: the vout_cal_offset command is used to apply a fixed offset voltage to the output voltage command value. this command is typically used by the user to ca librate a device in th e application circuit. data length in bytes: 2 data format: l16s type: r/w word default value: 0000h (0v) units: volts range : -4v to 4v vout_max (24h) definition: the vout_ max command sets an upper limit on the outp ut voltage the unit can command regardless of any other commands or combinations. the intent of this command is to prid e a safeguard against a user acci dentally setting the output vol tage to a possibly destructive level rather than to be the primary output overprotection. data length in bytes: 2 data format: l16u type: r/w word default value: 1.10xvout_command pin strap setting units: volts range: 0v to 4v vout_margin_high (25h) definition: sets the value of the v out during a margin high. this vout_margin_high command loads the unit with the voltage to which the output is to be changed when the operation command is set to ?margin high?. data length in bytes: 2 data format: l16u type: r/w word default value: 1.05 x vout_command pin strap setting units: volts range: 0v to vout_max vout_margin_low (26h) definition: sets the value of the v out during a margin low. this vout_margin_low comm and loads the unit with the voltage to which the output is to be changed when the op eration command is set to ?margin low?. data length in bytes: 2 data format: l16u type: r/w word default value: 0.95 x vout_command pin strap setting units: volts range: 0v to vout_max
zl9010m 38 fn8422.2 january 22, 2015 submit document feedback vout_transition_rate (27h) definition: this command sets the rate at which the output should change voltage when the device receives an operation command (margin high, margin low) that causes the output voltage to ch ange. the maximum possible positive value of the two data bytes indicates that the device should make the transition as quickly as possible. data length in bytes: 2 data format: l11 type: r/w word default value: ba00h (1v/ms) units : v/ms range: 0.1 to 4v/ms vout_droop (28h) definition: the vout_droop sets the effective load line (v/i slope) for the rail in which the device is used. it is the rate, in mv/a, at which the output voltage decreases (or increases) with increasing (or decreasing) output current for use with adaptive voltage positioning requirements and pa ssive current sharing schemes. data length in bytes: 2 data format: l11 type: r/w word default value: 0000h (0mv/a) units: mv/a range: 0 to 40 mv/a max_duty (32h) definition: sets the maximum allowable duty cycle of the switching frequency. data length in bytes: 2 data format: l11 type: r/w word default value: ead6h (90.75%) units: % frequency_switch (33h) definition: sets the switching frequency of the device. initial default value is defined by a pin strap and this value can be overridden by writing this command via pmbus. if an external sync is utilized, this value should be set as close as possible to the external clock value. the output must be disabled when writing this command. data length in bytes: 2 data format: l11 type: r/w word default value: pin strap setting units: khz range: 300khz to 1000khz
zl9010m 39 fn8422.2 january 22, 2015 submit document feedback interleave (37h) definition: configures the phase offset of a device that is sharing a comm on sync clock with other device s. a value of 0 for the number in group field is interpreted as 16, to allow for phase spreadin g groups of up to 16 devices. for current sharing rails, interl eave is used to set the initial phase of the rail. the current share devices th en automatically distribute their phase relative to the inter leave setting. data length in bytes: 2 data format: bit type: r/w word default value: set based on pin-strap pmbus address units: iout_cal_gain (38h) definition: sets the effective impedance across the current sense ci rcuit for use in calculating output current at +25c. data length in bytes: 2 data format: l11. type : r/w word default value: c20fh (2.06m ) units: m iout_cal_offset (39h) definition: used to null out any offsets in the output current sensing ci rcuit and to compensate for delayed measurements of current ramp due to i sense blanking time. data length in bytes: 2 data format: l 11. type : r/w word default value: bd4dh (-1.35a) units: a vout_ov_fault_limit (40h) definition: sets the v out overvoltage fault threshold. data length in bytes: 2 data format: l16u type: r/w word default value: 1.15xvout_command pin strap setting units: volts range: 0v to vout_max bits purpose value description 15:12 reserved 0 reserved 11:8 group number 0 to 15 sets a number to a group of interleaved rails 7:4 number in group 0 to 15 sets the number of rails in the group a value of 0 is interpreted as 16 3:0 position in group 0 to 15 sets position of the device's rail within the group
zl9010m 40 fn8422.2 january 22, 2015 submit document feedback vout_ov_fault_response (41h) definition: configures the v out overvoltage fault response. note that the device canno t be set to ignore this fault mode. the retry time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w byte default value: 80h (disable and no retry) units: n/a vout_uv_fault_limit (44h) definition: sets the v out undervoltage fault threshold. this fault is masked during ramp or when the device is disabled. data length in bytes: 2 data format: l16u type: r/w word default value: 0.8xvout_command pin strap setting units: volts range: 0v to vout_max bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault) 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device.
zl9010m 41 fn8422.2 january 22, 2015 submit document feedback vout_uv_fault_response (45h) definition: configures the v out undervoltage fault response. data length in bytes: 1 data format: bit type: r/w byte default value: 80h (disable, no retry) units: n/a iout_oc_fault_limit (46h) definition: sets the inductor peak overcurrent fault threshold. this li mit is applied to current measurement samples taken after the current sense blanking time has expired. a fault occurs after this limit is exceeded for the number of consecutive samples as d efined in mfr_config. data length in bytes: 2 data format: l11 type: r/w word default value: db00h (24a) units: a range: -24a to 24a iout_uc_fault_limit (4bh) definition: sets the inductor valley undercurrent fa ult threshold. this limit is applied to current measurement samples taken after the current sense blanking time has expired. a fault occurs after this limit is exceeded for the number of consecutive samples as d efined in mfr_config. data length in bytes: 2 data format: l11 type: r/w word default value: dd00h (-1xiout_oc_fault_limit, -24a) units: a range: -24a to 24a ot_fault_limit (4fh) definition: the ot_fault_limit command sets the temperature at which the device should indicate an over-temperature fault. note that the temperature must drop below ot_warn_limit to clear this fault. data length in bytes: 2 data format: l11 type: r/w word default value: ebe8h (+125 ? c) units: celsius range: 0 ? c to +175 ? c bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault) 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device.
zl9010m 42 fn8422.2 january 22, 2015 submit document feedback ot_fault_response (50h) definition: instructs the device on what action to take in response to an over-temperature fault. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type : r/w byte fault value: 80h (disable and no retry) units: n/a ot_warn_limit (51h) definition: the ot_warn_limit command sets the temperature at which the device should indicate an over-temperature warning alarm. in response to the ot_warn_limi t being exceeded, the device: sets the te mperature bit in status_word, sets the ot_warning bit in status_temperature and notifies the host. data length in bytes: 2 data format: l11. type : r/w word default value: eb70h (+110c) units: celsius range : 0 ? c to +175 ? c ut_warn_limit (52h) definition: the ut_warn_limit command set the temperature at which th e device should indicate an under-temperature warning alarm. in response to the ut_warn_limit being exceeded, the device: sets the temperature bit in status_word, sets the ut_warning bit in status_temperature and notifies the host. data length in bytes: 2 data format: l11. type : r/w word default value: e580h (-40c) units: celsius range : -55 ? c to +25 ? c bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault) 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device.
zl9010m 43 fn8422.2 january 22, 2015 submit document feedback ut_fault_limit (53h) definition: sets the temperature at which the device should indicate an under-temperature fault. note that the temperature must rise above ut_warn_limit to clear this fault. data length in bytes: 2 data format: l11 type: r/w word default value: e490h (-55c) units: celsius range: -55 ? c to +25 ? c ut_fault_response (54h) definition: instructs the device on what action to take in response to an under-temperature fault. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w byte default value: 80h (disable, no retry) units: n/a vin_ov_fault_limit (55h) definition: sets the vin overvoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w word default value: d3a0h (14.5v) units: volts range: 0v to 16v bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault) 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device.
zl9010m 44 fn8422.2 january 22, 2015 submit document feedback vin_ov_fault_response (56h) definition: configures the vin overvoltage fault response. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w byte default value: 80h (disable and no retry) units: n/a vin_ov_warn_limit (57h) definition: sets the vin overvoltage warning threshold as defined by the table below. in response to the _warn_limit being exceeded, the device: sets the none of the above and input bits in status _word, sets the vin__warning bit in status_input and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: d380h (14.0v) units: volts range : 0v to 16v vin_uv_warn_limit (58h) definition: sets the vin undervoltage warning threshold. if a vi n_uv_fault occurs, the input voltage must rise above vin_uv_warn_limit to clear the fault, which prides hysteresis to the fault threshold. in response to the uv_warn_limit being exceeded, the device: sets the none of the above and input bits in status_word, sets the vin_uv_warning bit in status_input and notifies the host. data length in bytes: 2 data format: l11 type : r/w word default value: ca40h (4.5v) units: volts range : 0v to 12v vin_uv_fault_limit (59h) definition: sets the vin undervoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w word default value: ca00h (4v) units: volts range: 0v to 12v bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault) 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device.
zl9010m 45 fn8422.2 january 22, 2015 vin_uv_fault_response (5ah) definition: configures the vin undervoltage fault response. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w byte default value: 80h (disable and no retry) units: n/a power_good_on (5eh) definition: sets the voltage threshold for power-good indication . power-good asserts when the output voltage exceeds power_good_on and de-asserts when the output voltage is less than vout_uv_fault_limit. data length in bytes: 2 data format: l16u type: r/w word default value: 0.9xvout_command pin strap setting units: volts ton_delay (60h) definition: sets the delay time from when the device is enabled to the start of vout rise. data length in bytes: 2 data format: l11 type: r/w word default value: ca80h (5ms) units: ms range: 0 to 500ms ton_rise (61h) definition: sets the rise time of vout after enable and ton_delay. data length in bytes: 2 data format: l11 type: r/w word default value: ca80h (5ms) units: ms range: 0 to 200ms bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault) 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device.
zl9010m 46 fn8422.2 january 22, 2015 toff_delay (64h) definition: sets the delay time from disable to start of vout fall. data length in bytes: 2 data format: l11 type: r/w word default value: ca80h (5ms) units: ms range: 0 to 500ms toff_fall (65h) definition: sets the fall time for vout after disable and toff_delay. data length in bytes: 2 data format: l11 type: r/w word default value: ca80h (5ms) units: ms range: 0 to 200ms status_byte (78h) definition : the status_byte command returns one byte of inform ation with a summary of th e most critical faults. data length in bytes: 1 data format: bit type: read byte default value: 00h units: n/a bit number status bit name meaning 7 busy a fault was declared because the device was busy and unable to respond. 6 off this bit is asserted if the unit is not prid ing power to the output, regardless of the reason, including simply not being enabled. 5 vout__ ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred.
zl9010m 47 fn8422.2 january 22, 2015 status_word (79h) definition: the status_word command returns two bytes of information wi th a summary of the unit's fa ult condition. based on the information in these bytes, the host can get more information by reading the appropriate status registers. the low byte of the status_word is the same register as the status_byte (78h) command. data length in bytes: 2 data format: bit type: read word default value: 0000h units: n/a status_vout (7ah) definition: the status_vout command returns one data byte with the status of the output voltage. data length in bytes: 1 data format: bit type: read byte default value: 00h units: n/a bit number status bit name meaning 15 vout an output voltage fault or warning has occurred. 14 iout/pout an output current or output power fault or warning has occurred. 13 input an input voltage, input current, or input power fault or warning has occurred. 12 mfg_specific a manufacturer specific fault or warning has occurred. 11 power_good# the power_good signal, if present, is negated. 10 fans a fan or airflow fault or warning has occurred. 9 other a bit in status_other is set. 8 unknown a fault type not given in bits 15:1 of the status_word has been detected. 7 busy a fault was declared because the device was busy and unable to respond. 6 off this bit is asserted if the unit is not priding power to the output, regardless of the reason, including simply not being enabled. 5 vout__ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred. bit number status bit name meaning 7 vout__ov_fault indicates an output overvoltage fault. 6 vout__warning indicates an output overvoltage warning. 5 vout_uv_warning indicates an output undervoltage warning. 4 vout_uv_fault indicates an output undervoltage fault. 3 vout_max_warning an attempt has been made to set the output voltage to value higher than allowed by the vout_max command. 2ton_max_fault indicates t on max fault 1 toff_max_fault indicates t off max fault 0 vout_tracking_error indicates v out tracking error ( note 24 ). note: 24. the conditions that cause the v out tracking error bit to be set is defined by each device ma nufacturer. this status bit is intended to allow the device to notify the host that there was error in output voltage tracking during the most recent power or power down event.
zl9010m 48 fn8422.2 january 22, 2015 status_iout (7bh) definition: the status_iout command returns one data byte with the status of the output current. data length in bytes: 1 data format: bit type: read byte default value: 00h units: n/a status_input (7ch) definition: the status_input command returns input volt age and input current status information. data length in bytes: 1 data format: bit type: read byte default value: 00h units: n/a bit number status bit name meaning 7 iout_oc_fault an output overcurrent fault has occurred. 6 iout_oc_lv_fault an output overcurrent and low voltage fault has occurred. 5 iout_uc_warning an output ov ercurrent warning has occurred. 4 iout_uc_fault an output undercurrent fault has occurred. 3 ishare_fault an current share fault occurred ( note 25 ). 2 power_limiting_mode_fault an pout limiting mode fault occurred ( note 26 ). 1 pout_op_fault an pout over power fault occurred. 0 pout_op_warning indicates pout over power warning. notes: 25. the conditions that cause the current share fault bit to be set are defined by each device manufacturer. 26. [2] the bit is to be asserted when the unit is operating with the output in constant power mode at the power set by the pout _max command. bit number status bit name meaning 7 vin__fault an input overvoltage fault has occurred. 6 vin__warning an input overvoltage warning has occurred. 5 vin_uv_warning an input undervoltage warning has occurred. 4 vin_uv_fault an input undervoltage fault has occurred. 3 unit off for low input voltage unit is off for insufficient input voltage ( note 27 ). 2 iin oc fault an iin overcurrent fault occurred. 1 iin oc warning an iin overcurrent warning occurred 0 pin op warning an pin overpower waning occurred. note: 27. either the input voltage has never exceeded the input turn-on threshold or if the unit did start, the input voltage decrease d below the turn-off threshold.
zl9010m 49 fn8422.2 january 22, 2015 status_temp (7dh) definition: the status_temp command returns one byte of information with a summary of any temperature related faults or warnings. data length in bytes: 1 data format: bit type: read byte default value: 00h units: n/a status_cml (7eh) definition: the status_cml command returns one byte of information wi th a summary of any communic ations, logic and/or memory errors. data length in bytes: 1 data format: bit type: read byte default value: 00h units: n/a bit number status bit name meaning 7 ot_fault an over-temperature fault has occurred. 6 ot_warning an over-temperature warning has occurred. 5 ut_warning an under-temperature warning has occurred. 4 ut_fault an under-temperature fault has occurred. 3:0 n/a these bits are not used. bit number meaning 7 invalid or unsupported pmbus command was received. 6 the pmbus command was sent with invalid or unsupported data. 5 a packet error was detected in the pmbus command. 4 memory fault detected ( note 28 ). 3 processor fault detected ( note 29 ). 2reserved . 1 a pmbus command tried to write to a read-only or protected comma nd, or a communication fault other than the ones listed in thi s table has occurred. 0 other memory or logic fualt has occurred ( note 30 ). notes: 28. the conditions that cause the memory fault detected bit to be set and the response this condition, are defined by each devic e manufacturer. one example of an error that would cause this bit to be set is a crc of the memory that does not match the initial crc value. 29. the conditions that cause the processor fa ult detected bit to be set and the response this condition, are defined by each de vice manufacturer. 30. the conditions that cause the other memory or logic fault detected bit to be set and the response this condition, are define d by each device manufacturer.
zl9010m 50 fn8422.2 january 22, 2015 status_mfr_specific (80h) definition : returns the communication, logic and memory specific status. data length in bytes: 1 data format: bit type: read byte default value: 00h units: n/a read_vin (88h) definition: returns the input voltage reading. data length in bytes: 2 data format: l11 type: read word units: volts read_vout (8bh) definition: returns the output voltage reading. data length in bytes: 2 data format: l16u type: read word units: volts read_iout (8ch) definition: returns the output current reading. data length in bytes: 2 data format: l11 type: read word default value: n/a units: a read_temperature_1 (8dh) definition: returns the controller juncti on temperature reading from internal temperature sensor. data length in bytes: 2 data format: l11 type: read word units: c read_temperature_2 (8eh) definition: returns the temperature reading from the extern al temperature device connected to xtemp pins. data length in bytes: 2 data format: l11 type: read word units: c bit field name meaning 7:6 reserved reserved 5 reserved reserved 4 reserved reserved 3 tsw loss of external clock synchronization has occurred. 2 reserved reserved 1 reserved reserved 0 reserved reserved
zl9010m 51 fn8422.2 january 22, 2015 read_duty_cycle (94h) definition: reports the actual duty cycle of the converter during the enable state. data length in bytes: 2 data format: l11 type: read word units: % read_frequency (95h) definition: reports the actual switching frequency of the converter during the enable state. data length in bytes: 2 data format: l11 type: read word units: khz pmbus_revision (98h) definition: returns the revision of the pmbus implemented in the device data length in bytes: 1 data format: hex type: read byte default value: 01h units: n/a mfr_id (99h) definition: mfr_id sets user defined identification. the sum tota l of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a mfr_model (9ah) definition: mfr_model sets a user defined model. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_revision (9bh) definition: mfr_revision sets a user defined revision. the sum tota l of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a
zl9010m 52 fn8422.2 january 22, 2015 mfr_location (9ch) definition: mfr_location sets a user defined location identifier. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_date (9dh) definition: mfr_date sets a user defined date. the sum total of char acters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per comm and cannot exceed 128 characters . this limitation includes multiple writes of this command before a store command. to clea r multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a reference: n/a mfr_serial (9eh) definition: mfr_serial sets a user defined serializ ed identifier. the sum total of characte rs in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a user_data_00 (b0h) definition: user_data_00 sets a user defined da ta. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a
zl9010m 53 fn8422.2 january 22, 2015 auto_comp_config (bch) definition: controls configuration of auto compensation features. data length in bytes: 1 data format: cus type: r/w byte default value: 69h units: n/a auto_comp_control (bdh) definition: causes the auto comp algorithm to initiate, if the auto comp featur e is enabled in auto_comp_config. data length in bytes: 1 data format: bit type: send byte default value: units: n/a deadtime_max (bfh) definition: sets the maximum deadtime value for the pwmh and pwml output s. this limit applies during frozen or adaptive deadtime algorithm modes data length in bytes: 2 data format: cus type: r/w word default value: 3838h (56ns) range: 0 to 60ns units: ns bits purpose value description 7:4 auto comp gain percentage g scale the gain of the auto compensation results by a factor of (g+1)*10%, where 0 = g = 9. g = 0 yields lowest jitter; g = 9 yields tightest transient response. 3power good assertion 0use pg_delay 1 assert pg after auto comp completes 2auto comp store 0 do not store auto comp results 1 store auto comp results for use on future ramps 1:0 auto comp mode 0 off (disabled). compensation stored in pid_taps will be used. 1 once (results are storable) 2 repeat every ~1 second (only the first results are storable) 3 repeat every ~1 minute (only the first results are storable) bit number purpose value meaning 15 n/a 0 not used 14:8 sets the maximum h-to-l deadtime h limits the maximum allowed h-to-l deadtime when using the adaptive deadtime algorithm. deadtime = hns (signed). 7n/a 0 not used 6:0 sets the maximum l-to-h deadtime l limits the maximum allowed l-to-h deadtime when using the adaptive deadtime algorithm. deadtime = lns (signed).
zl9010m 54 fn8422.2 january 22, 2015 mfr_config (d0h) definition: configures several manufacturer-level features. data length in bytes: 2 data format: bit type: r/w word default value: 6a11h units: n/a bit number purpose value meaning 15:11 current sense blanking delay d sets the delay, d, in 32ns steps 10:8 current sense fault count c sets the number of consecut ive oc or uc violations required for a fault to 2c+1. 7 enable xtemp measurements 0 no temperature measurements are performed on xtemp 1 temperature measurements are performed on xtemp 6 temperature sensor control ( note 31 ) 0 the internal temperature sensor is used for warning and fault checks 1 an external 2n3904 npn on xtemp is used for warning and fault checks 5:4 current sense control 00 current sense uses gnd-re ferenced, down-slope sense 01 current sense uses vout-ref erenced, down-slope sensing 10 current sense uses vout-referenced, up-slope sensing 11 reserved 3 nlr during ramp 0wait for pg 1always on 2 alternate ramp control 0 alternate ramp disabled 1 alternate ramp enabled 1 pg pin output control 0 pg is open-drain 1 pg is push-pull 0 sync pin output control 0 sync is open-drain 1sync is push-pull note: 31. when selecting xtemp (bit 6), be sure to have the xtemp enabled in bit 7.
zl9010m 55 fn8422.2 january 22, 2015 user_config (d1h) definition: configures several user-level features. data length in bytes: 2 data format: bit type: r/w word default value: 2011h units: n/a bit purpose value description 15:14 minimum duty cycle n sets the minimum duty cycle ((n+1)/(2 8 )) during a ramp when ?minimum duty cycle? (bit 13) is enabled. for example, if minimum duty cycle input n is set to 3, the minimum duty cycle is (3+1)/(2^8) = (1/64). 13 minimum duty cycle control 0 minimum duty cycle is disabled. 1 minimum duty cycle is enabled. 12 reserved - reserved 11 sync time-out enable 0 sync output remains on after device is disabled. 1 sync turns off 500ms after device is disabled. 10 reserved - reserved 9 pid feed-forward control 0 pid coefficients are corre cted for vdd variations. 1 pid coefficients are not co rrected for vdd variations. 8 fault spreading mode 0 if sequencing is disabled, this device will ignore faults from other devices. if sequencing is enabled, the devices will sequence do wn from the failed device outward. 1 faults received from any device selected by the ddc_group command will cause this device to shut down immediately. 7 reserved - reserved 6 sync input mode 0 pin strap setting. 1external sync. 5 sync pin configure 0 configure the sync pin as an input-only. 1 output external signal. 4 reserved - reserved 3 reserved - reserved 2 off low-side c 0 the low-side drive is off when device is disabled. 1 the low-side drive is on when device is disabled. 1:0 standby mode 00 enter low-power mode when device is disabled (no read_xxxx data available). 01 monitor for faults when device is disabled (read_xxxx data available). 10 reserved 11 monitor for faults using pulsed mode (read_xxxx data available upon read command).
zl9010m 56 fn8422.2 january 22, 2015 ishare_config (d2h) definition: configures the device for current sharing communication over the ddc bus. data length in bytes: 2 data format: bit type: r/w word default value: 0000h units: n/a ddc_config (d3h) definition: configures ddc addressing. data length in bytes: 2 data format: bit type: r/w word default value: 0001h units: n/a power_good_delay (d4h) definition: sets the delay applied between the output exceeding the pg threshold (power_good_on) an d asserting the pg pin. the delay time can range from 0ms up to 500s, in steps of 125ns. a 1ms minimum configured value is recommended to apply proper de-bounce to this signal. data length in bytes: 2 data format: l11 type: r/w word default value: ba00h(1ms) units: ms range: 0 to 5s bit purpose value description 15:8 ishare ddc id 0 to 31 (0x00 to 0x1f) sets the current share rail?s ddc id for each device within a current share rail. set to the same ddc id as in ddc_config. this ddc id is used for sequencing and fault spreading when used in a current share rail. 7:5 number of members 0 to 7 number of devices in current share rail -1. example: 3 device current share rail, use 3 ? 1 = 2 4:2 member position 0 to 7 position of device within current share rail. 1 reserved 0 reserved 0 i-share control 1 device is a member of a current share rail. 0 device is not a member of a current share rail. bit field name value description 15:13 reserved 0 reserved. 12:8 broadcast group 0 to 31 group number used for broadc ast events. (i.e., broadcast enable and broadcast margin) set this number to the same value for all rail s/devices that should respond to each other?s broadcasted event. this function is enable d by the bits 15 and 14 in the misc_config command. 7:6 reserved 0 reserved. 5ddc tx inhabit 0ddc transmission. 1 ddc transmission enabled. 4:0 rail id 0 to 31 (00 to 1fh) sets the rail?s ddc id for sequencing and fault spreading. for the current-sharing applications, set th is value the same as the id value in ishare_config for all devices in the current sharing rail.
zl9010m 57 fn8422.2 january 22, 2015 pid_taps (d5h) definition: configures the control loop compensator coefficients. data length in bytes: 9 data format: cus units: n/a type: r/w default value: auto comp stores when algorithm is initiated during start up. when auto comp is disabled pid_taps can be stored via pmbus. the pid algorithm implements the following z-domain function in equation 10 : the coefficients a, b and c are represented using a pseudo-floating point format similar to the v out parameters (with the addition of a sign bit), defined as equation 11 : where m is a two-byte unsigned mantissa, s is a sign-bit and e is a 7-bit two?s-complement signed integer. the 9-byte data fiel d is defined in table. s is stored as the msb of the e byte. inductor (d6h) definition: informs the device of circuit?s inductor value. this is used in adaptive algorithm calculations relating to the inductor rippl e current. data length in bytes: 2 data format: l11 type: r/w word default value: b200h (0.5h) units: h byte purpose definition 8 tap c - e coefficient c exponent + s 7 tap c - m [15:8] coefficient c mantissa, high-byte 6 tap c - m [7:0] coefficient c mantissa, low-byte 5 tap b - e coefficient b exponent + s 4 tap b - m [15:8] coefficient b mantissa, high-byte 3 tap b - m [7:0] coefficient b mantissa, low-byte 2 tap a - e coefficient a exponent + s 1 tap a - m [15:8] coefficient a mantissa, high-byte 0 tap a - m [7:0] coefficient a mantissa, low-byte note: 32. data bytes are transmitted on the pmbus in the order of byte 0 through byte 8. abz 1 C cz 2 C ++ 1z 1 C C ------------------------------------------- - (eq. 10) a1 C ?? s 2 e m ? ? = (eq. 11)
zl9010m 58 fn8422.2 january 22, 2015 nlr_config (d7h) definition: configures the non-linear resp onse (nlr) control parameters. data length in bytes: 4 data format: bit type: r/w block default value: 00000000h units: n/a ovuv_config (d8h) definition: configures the output voltage ov and uv fault detection feature. the default value of 00h is recommended. data length in bytes: 1 data format: bit type: r/w default value: 00h units: n/a xtemp_scale (d9h) definition: sets a scalar value that is used for calibrating the external temperature. the constant is applied in equation 1 to produce th e read value of xtemp via the p mbus command read_temperature_2. data length in bytes: 2 data format: l11 type: r/w default value: ba00h (1c) units: c note: this value must be equal to 1. bit field name value description 31:30 outer threshold multiplier 0 sets multiplier of i nner threshold for outer thre shold setting, o*li and o*ui 29:27 nlr comparator threshold: load ing-inner li sets inner threshold for a loading event to ~0.5%*(li+1)*vout. 26:24 nlr comparator threshold: unloading-inner ui sets in ner threshold for an unloading event to ~0.5%*(ui+1)*vout . 23:20 loading-outer threshold max correction time lot sets outer threshold, maximum correction time for a loading event to lot*tsw/64(s). 19:16 loading-inner threshold max correctio n time lit sets inner threshold, maximum correction time for a loading event to lit*tsw/64(s). 15:12 unloading-outer threshold max correction time uot sets outer threshold, maximum correction time for an unloading event to uot*tsw/64(s). 11:8 unloading-inner threshold max correction time uit sets inner threshold, maximum correction time for an unloading event to uit*tsw/64(s). 7:4 load blanking time control lb sets nlr blanking time for a loading event. 3:0 unload blanking time co ntrol ub sets nlr blanking time for an unloading event. table 16. loading/unloading blanking times lb or ub 0123456789101112131415 t sw / 64 units 1 2 3 5 9 17 33 49 65 81 97 129 161 177 193 225 bit purpose value definition 7 controls how an ov fault response shutdown sets the output driver state 0 an ov fault does not enable the low-side power device 1 an ov fault enables the low-side power device 6:4 not used 0 not used 3:0 defines the number of co nsecutive limit violations required to declare an ov or uv fault n n+1 consecutive ov or uv violations initiate a fault response et xtemp_offs e xtemp_scal 1 mperature externalte rature_2 read_tempe ? ? ? ? ? ? ? ? ? ? ?
zl9010m 59 fn8422.2 january 22, 2015 xtemp_offset (dah) definition: sets an offset value that is used for ca librating the external temperature. the cons tant is applied in equation 2 to produce the read value of xtemp via the pmbus command read_temperature_2. data length in bytes: 2 data format: l11 type: r/w word default value: 8000h (0c) units: c tempco_config (dch) definition: configures the correction factor and temperature measurement source when performing temperature coefficient correction for current sense. tempco_config values are applied as negative correction to a positive temperature coefficient. data length in bytes: 1 data format: cus type: r/w byte default value: 28h (4000ppm/c) units: n/a to determine the hex value of the tempco correction fa ctor (tc) for current scale of a power stage using r dc(on) current sensing, first determine the temperature coefficient of resistance for the conductor, ? . this is found with equation 12 : where: r = conductor resistance at temperature ?t? r ref = conductor resistance at reference temperature t ? = temperature coefficient of resistance for the conductor material t = temperature measured by temperature sensor, in c t ref = reference temperature that ? is specified at for the conductor material after ? is determined, convert the value in units of 100ppm/ c. this value is then converted to a hex value with equation 13 . typical values: copper = 3900ppm/c (27h), silicon = 4800ppm/c (30h) range: 0 to 6300ppm/c bit purpose value definition 7 selects the temp sensor source for tempco correction 0 selects the internal temperature sensor 1 selects the xtemp pin for temperature measurements 6:0 sets the tempco correction in units of 100ppm/c for iout_cal_gain tc r sen(dcr) =iout_cal_gain*(1+tc*(t-25)) where r sen = resistance of sense element et xtemp_offs e xtemp_scal 1 mperature externalte rature_2 read_tempe ? ? ? ? ? ? ? ? ? ? ? ? r ref r C r ref t ref t C ?? --------------------------------------------- - = (eq. 12) tc ? 10 6 ? 100 ------------------- = (eq. 13)
zl9010m 60 fn8422.2 january 22, 2015 deadtime (ddh) definition: sets the non-overlap between pwm transitions using a 2-byte da ta field. the most significant byte controls the high-side to low-side deadtime value as a single 2?s-co mplement signed value in units of ns. the least significant byte controls the low-sid e to high-side deadtime value. positive values imply a non-overlap of the fet drive on-times. negative values imply an overlap of th e fet drive on-times. the device will operate at the deadtime values wr itten to this command when adap tive deadtime is disabled, betw een the minimum deadtime specified in deadtime_config and the ma ximum deadtime specified in deadtime_max. when switching from adaptive deadtime mode to frozen mode (by writing to bit 15 of deadtime_config) the frozen deadtime will be whatever the last deadtime was before the device switches to frozen deadtime mode. data length in bytes: 2 data format: cus type: r/w word default value: 1414h (h-l = 20ns, l-h = 20ns) units: ns range: -15ns to 60ns deadtime_config (deh) definition: configures the deadtime optimization mode. also sets the minimum deadtime value for the adaptive deadtime mode range. data length in bytes: 2 data format: cus type: r/w word default value: 8686h (adaptive deadtime disabled) units: n/a bit purpose value description 15 sets the high to low transition deadtime mode 0 adaptive h-to-l deadtime control. 1 freeze the h-to-l deadtime. 14:8 sets the minimum h-to-l deadtime 0-126d limits the minimum allowed h-to-l deadtime when using the adaptive deadtime algorithm (2ns resolution). 7 sets the low to high transition deadtime mode 0 adaptive l-to-h deadtime control. 1 freezes the l-to-h deadtime. 6:0 sets the minimum l-to-h deadtime 0-126d limits the minimum allowed l-to-h deadtime when using the adaptive deadtime algorithm (2ns resolution).
zl9010m 61 fn8422.2 january 22, 2015 submit document feedback sequence (e0h) definition: identifies the rail ddc id of the prequel and sequel rails wh en performing multi-rail sequencing. the device will enable its output when its en or operation enable states, as defined by on_off_config, is set and the prequel device has issued a power-go od event on the ddc bus. the device will disable its output (using the programmed delay values) when the sequel device has issued a power-down event on the ddc bus. the data field is a two-byte value. the most-significant byte co ntains the 5-bit rail ddc id of the prequel device. the least-s ignificant byte contains the 5-bit rail ddc id of the sequel device. the most significant bit of each byte contains the enable of the preq uel or sequel mode. this command overrides the corresponding sequence configuration set by the config pin settings. data length in bytes: 2 data format: bit type: r/w word default value: 0000h (prequel and sequel disabled) track_config (e1h) definition: configures the voltage tracking modes of the device. data length in bytes: 1 data format: bit type: r/w byte default value: 00h (tracking disabled) ddc_group (e2h) definition: this command sets which rail ddc ids a de vice should listen to for fault spreading information. a device can follow multiple ddc id rails. example is provided in following table. the device/rail?s own ddc id shou ld not be set within the ddc_group command for that device/rail. all devices in a current share rail must shut down for the rail to report a shutdown. if fault spread mode is enabled in user_config (bit 8 set to 1) , the device will immediately shut down if one of its ddc_group members fail. the device/rail will attempt its configured restart only after all devices/rails within the ddc_group have cleare d their faults. if fault spread mode disabled in user_config (bit 8 cleared to 0), the device will perform a sequenced shutdown as defined by t he sequence command setting. the rails/devices in a sequencing set on ly attempt their configured rest art after all faults have cle ared within the ddc_group. if fault spread mode is disabled and sequencing is also disabled, the device will ignore faults from othe r devices and stay enabled. data length in bytes : 4 data format: bit type: r/w default value: 00000000h (ignore fault spread) bit field name value setting description 7 enables voltage tracking 0 disable tracking is disabled 1 enable tracking is enabled 6:3 reserved - reserved reserved 2 tracking ratio control 0 100% output tracks 100% ratio of vtrk input 1 50% output tracks 50% ratio of vtrk input 1 tracking upper limit 0 target voltage output voltage is limited by target voltage 1 vtrk voltage output voltage is limited by vtrk voltage 0ramp-up behavior 0 track after pg the output is not allowe d to track vtrk down before power-good 1 track always the output is allowed to track vtrk down before power-good ddc id configuration ddc_group description 0 3xzl9010m current sharing 0000000ah this ra il will listen to rail-1 and rail-3. 1 2xzl9010m current sharing 00000004h th is rail will listen to rail-2. 2 1xzl9010m single phase 00000000h this rail will ignore fault spread. 3 1xzl9010m single phase 00000002h this rail will listen to rail-1.
zl9010m 62 fn8422.2 january 22, 2015 submit document feedback device_id (e4h) definition: returns the 16-byte (character) device identifier string. data length in bytes: 16 data format: asc type: read block default value: current firmware revision mfr_iout_oc_fault_response (e5h) definition: configures the i out overcurrent fault response as defined by the following table. sets the overcurrent status bit in status_iout. data length in bytes: 1 data format: bit type: r/w byte default value: 80h (disable and no retry) units: n/a mfr_iout_uc_fault_response (e6h) definition: configures the iout undercurrent fault response as defined by the table below. sets the undercurrent status bit in status_iout. data length in bytes: 1 data format: bit type: r/w byte default value: 80h (disable and no retry) units: n/a bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault), 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device. bit field name value description 7:6 response behavior: sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 continuous operation (ignore fault), 01 delay, disable and retry delay time is specified by bits[2:0] and retry attempt is specified in bits[5:3]. 10 disable and retry according to the setting in bits[5:3]. 11 output is disabled while the fa ult is present. output is enab led when the fault condition no longer exists. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 the pmbus device attempts to restart the nu mber of times set by these bits. the time between the start is set by the value in bits[2:0]. 111 attempts to restart continuously, without checking if the fault is still presen t, until it is disabled, bias power is removed, or another fault condition causes the unit to shut down. 2:0 retry and delay time 000-111 this time count is used for both the amount of time between re try attempts and for the amount of time a rail is to delay its response after a fault is detected. the retry time and delay time units are defined by the type of fault within each device.
zl9010m 63 fn8422.2 january 22, 2015 submit document feedback iout_avg_oc_fault_limit (e7h) definition: sets the iout average overcurrent fault threshold. for down-slo pe sensing, this corresponds to the average of all the current samples taken during the (1-d) time interval, excluding the curren t sense blanking time (which o ccurs at the beginning of the 1 -d interval). for up-slope sensing, this corresponds to the averag e of all the current samples take n during the d time interval, e xcluding the current sense blanking time (which occurs at the beginning of the d interval). this feature shares the oc fault bit operation ( in status_iout) and oc fault response with iout_ oc_fault_limit. data length in bytes: 2 data format: l11 type: r/w word default value: d3c0h (15a) units: a iout_avg_uc_fault_limit (e8h) definition: sets the iout average undercurrent faul t threshold. for down-slope sensing, this corresponds to the average of all the current samples taken during the (1-d) time interval, excluding the current sense blanki ng time (which occurs at the beginning of the 1-d interval). for up-slope sensing, this corresponds to the average of all the current samples taken during the d time interva l, excluding the current sense blanking time (w hich occurs at the beginning of the d inte rval). this feature shares the uc fault b it operation (in status_iout) and uc faul t response with iout_ uc_fault_limit. data length in bytes: 2 data format: l11 type: r/w word default value: d440h (-15a) units: a misc_config (e9h) definition: sets options pertaining to advanced features. data length in bytes: 2 data format: bit type: r/w word units: n/a default value: 2000h bits purpose value description 15 broadcast margin (see ddc_config) 0 disabled 1enable 14 broadcast enable (see ddc_config) 0 disabled 1enable 13 phase enable select 0 use ph_en pin to add/drop current-share phases. 1 use phase_control command to add/drop phases. 12 reserved - reserved 11:10 reserved - reserved 9 reserved - reserved 8 reserved - reserved 7 reserved - reserved 6 diode emulation 0 disabled 1 enabled, enter diode emulation at light loads to improve efficiency 5:3 reserved - reserved 2 minimum gl pulse 0 disabled 1 enabled, gl pulse width limited to 10%*t sw minimum during diode emulation. 1 snapshot 0 disabled 1enable 0 reserved - reserved
zl9010m 64 fn8422.2 january 22, 2015 submit document feedback snapshot (eah) definition: the snapshot command is a 32-byte read-bac k of parametric and status values. it a llows monitoring and status data to be stored to flash either during a fault condit ion or via a system-defined time using the snapshot_control command. in case of a f ault, last updated values are stored to the flash memory. use snapshot_control command to read stored values. data length in bytes: 32 data format: bit type: block read blank_params (ebh) definition: returns a 16-byte string which indicates which parameter values were either retrieved by the last restore operation or have been written since that time. reading blank_params immediately after a restore op eration allows the user to determine whic h parameters are stored in that store. inde x to read blank_param is provided in ? ? pmbus command summary ? on page 28 . one indicates the parameter is not present in the store and has not been written since the restore operation. data length in bytes: 16 data format: bit type: block read default value: ff?ffh units: n/a phase_control (f0h) definition: this command controls phase adding/dropping wh en the device is setup for current sharing. data length in bytes: 1 data format: bit type: r/w byte default value: 00h byte number value pmbus command format 31:22 reserved reserved 00h 21 manufacturer specific status byte status_mfr_specific (80h) byte 20 cml status byte status_cml (7eh) byte 19 temperature status byte status_temperature (7dh) byte 18 input status byte status_input (7ch) byte 17 i out status byte status_iout (7bh) byte 16 v out status byte status_vout (7ah) byte 15:14 switching frequency read_frequency (95h) l11 13:12 external temperature read_external_temp (8eh) l11 11:10 internal temperature read_internal_temp (8dh) l11 9:8 duty cycle read_duty_cycle (94h) l11 7:6 peak current n/a l11 5:4 load current read_iout (8ch) l11 3:2 output voltage read_vout (8bh) l16u 1:0 input voltage read_vin (88h) l11 value d value description 00h the device phase is disabled or dropped 01h 01h the device phase is active or added
zl9010m 65 fn8422.2 january 22, 2015 submit document feedback snapshot_control (f3h) definition: writing a 01 will cause the device to copy the current snap shot values from nvram to the 32-byte snapshot parameters. writing a 02 will cause the device to write the current snapshot values to nvram. read from nvram (writing a 01) does not work if snapshot is enabled in misc_config. to read from nvram, the device has to be disabled. data length in bytes: 1 data format: bit type: r/w byte restore_factory (f4h) definition: restores the device to the hard-coded factory default values and pin strap definitions. the device retains the default and user stores for restoring. security level is changed to level 1 following this command. data length in bytes: 0 data format: n/a type: send byte default value: n/a units: n/a security_level (fah) definition: the device provides write protection for individual command s. each bit in the unprotect parameter controls whether its corresponding command is writeable (commands are always readable). if a command is no t writeable, a password must be entered in order to change its parameter (i.e., to enable writes to that co mmand). there are two types of passwords, public and private. t he public password provides a simple lock-and-key protection against accide ntal changes to the device. it would typically be sent to the device in the application prior to making changes. private passwords allow commands marked as non-writeable in the unprotect parameter to be changed. private passwords are intended for protecting defaul t-installed configurations and wo uld not typically be used in t he application. each store (user and default) can have its own un protect string and private password. if a command is marked as non-writeable in the default unprotect parameter (its correspondi ng bit is cleared), the private password in the default store must be sent in order to change that command. if a command is writeable according to the default unprotect parameter, it may still b e marked as non-writeable in the user store unprotect parameter. in this case, the user private password can be sent to make the command writeable. the device supports four levels of security. each level is designed to be used by a particular class of users, ranging from mod ule manufacturers to end users, as discussed below. levels 0 and 1 correspond to the public password. all other levels require a pr ivate password. writing a private password can only raise the security level. writing a public password will reset the level down to 0 or 1. figure 27 shows the algorithm used by the device to dete rmine if a particular command write is allowed. security level 3 ? module vendor level 3 is intended primarily for use by module vendors to protect device configurations in the default store. clearing a unpro tect bit in the default store implies that a command is writeable only at level 3 and above. the device?s security level is raised to le vel 3 by writing the private password value previously stored in the defaul t store. to be effective, the module vendor must clear the un protect bit corresponding to the store_default_all and restore_default commands. otherwise, level 3 protection is ineffective since the entire store could be replaced by the user, including the enclosed private password. security level 2 ? user level 2 is intended for use by the end user of the device. clea ring a unprotect bit in the user store implies that a command is writeable only at level 2 and above. the device?s security leve l is raised to level 2 by writing the private password value pre viously stored in the user store. to be effective, the user must clear the unprotect bit corresponding to the store_user_all, restore_default_all, store_default_all and restore_default co mmands. otherwise, level 2 protection is ineffective since the entire store could be replaced, including the enclosed private password. value description 01h move parametric and status values from flash to the ram. 02h move latest parametric and status values from ram to the flash.
zl9010m 66 fn8422.2 january 22, 2015 submit document feedback security level 1 ? public level 1 is intended to protect against accidental changes to ordi nary commands by providing a gl obal write-enable. it can be us ed to protect the device from erroneous bus operations. it provides a ccess to commands whose unprotect bit is set in both the default and user store. security is raised to level 1 by writing the publ ic password stored in the user store using the public_password command. the public password stored in the default store has no effect. security level 0 - unprotected level 0 implies that only commands which ar e always writeable (e.g., public_password) are available. this represents the lowest authority level and hence the most protected state of the device. the level can be reduced to 0 by using public_password to wri te any value which does not match the stored public password data length in bytes: 1 data format: hex type: read byte default value: 01h figure 27. algorithm used to determine when a command is writeable
zl9010m 67 fn8422.2 january 22, 2015 submit document feedback private_password (fbh) definition: sets the private password string. data length in bytes: 9 data format: ascii. iso/iec 8859-1 type: r/w block default value: 000..00h public_password (fch) definition: sets the public password string. data length in bytes: 4 data format: ascii. iso/iec 8859-1 type: r/w block default value: 00...00h unprotect (fdh) definition: sets a 256-bit (32-byte) parameter which identifies which co mmands are to be protected against write-access at lower security levels. each bit in this parameter corresponds to a co mmand according to the command?s code. the command with a code o f 00h (page) is protected by the least signif icant bit of the least significant byte, followed by the command with a code of 01h and so forth. note that all possible commands have a corresponding bit regardless of whether they are protected or supported by the de vice. clearing a command?s unprotect bit indicates that write access to that command is only allowed if the device?s security level h as been raised to an appropriate level. the unprotect bits in the default store require a security level 3 or greater to be writea ble. the unprotect bits in the user store require a security level of 2 or higher. data length in bytes: 32 data format: cus type: block r/w default value: ff...ffh firmware revision history firmware revision code change description note fe03 not recommended for a new design. fe04 1. vin_ov_warn_limit = 14.0v 2. vin_uv_fault_limit = 4.0v 3. ot_warn_limit = +110c 4. ot_fault_limit = +125c 5. vin_uv_warn_limit = 4.5v 6. deadtime = 1414h (h-l = 20ns, l-h = 20ns) 7. deadtime_max = 3838h (max h-l = 56ns, max l-h = 56ns) recommended for a new design.
zl9010m 68 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8422.2 january 22, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the intersil website to make sure you have the latest revision. date revision change january 22, 2015 fn8422.2 updated table 4 on page 16 with additional values. october 30, 2014 fn8422.1 removed ?zilker la b? references throughout the datasheet. under features on page 1 added: overcurrent/undercurrent protection. updated figure 1 on page 1: removed (epad), rtn and i 2 c. removed an2033 throughout the datasheet. added part numbers zl9010mairz and ZL9010MEVAL1Z to ordering information table on page 6. ordering information table on page 6: added firmware revision column and note 4. on page 6 added part number key. removed i 2 c throughout the document. pin description table on page 3 changes: pin# a5: added a text: a pull-up resistor is required for this application. pin# e1: added see table 8 for setting switching frequency. added refer to ?layout guide section? to pin numbers ci, d1 and fb+. changed the type from ?i? to ?test?. added a text to fb+: ?this pin is noise sensitive?. on page 24; added ?active current sharing? section. on page 25: added the latest snapshot parameter capture. added pmbus command section. completing a power supply design section on page 14: replaced i 2 c address, i 2 c clock and i 2 c host to pmbus though out the datasheet. on page 67: added firmwa re revision history. ?firmware revision history? on page 67 u pdated codes from fc03, fc04 to fe03, fe04. march 5, 2013 fn8422.0 initial release
zl9010m 69 fn8422.2 january 22, 2015 submit document feedback package outline drawing y32.17.2x11.45 32 i/o 17.2mm x 11.45mm x 2.5mm hda module rev 1, 11/12 bottom view side view top view detail a detail b 1.0mmx1.0mm represents the basic land grid pitch. 2. all dimensions are in millimeters. 1. notes: 27 is the total number of i/o (excluding large pads). all 27 i/os are centered in a fixed row and column matrix at 1.0mm pitch bsc. dimensioning and tolerancing per asme y14.5m-1994. tolerance for exposed dap e dge location dimension on page 2 is 0.1mm. 3. 4. 5. terminal tip 3 see detail b c = 0.35 see detail a datum a datum b 11.45 17.20 0.025 max 2.50 max 7.00 10.400.15 10.00 0.900.10 16.500.15 0.180.10 0.95 1.00 27x(0.600.05) 1.00 0.550.10 0.550.10 27x(0.600.05) 1.00 2.00 0.10 c seating plane 2x terminal #a1 index area 2x a b pin a1 indicator 0.10 c 0.10 c k l 3 9 10 6 8 7 4 5 e d j h g f c b a 2 1 0.10 c a b 0.10 c a b 0.10 c 0.08 c 0.10 c a b 0.05 c 3
zl9010m 70 fn8422.2 january 22, 2015 submit document feedback centerline position detail s for the 5 exposed daps size details for the 5 exposed daps bottom view bottom view 0.38 4.20 4.38 3.88 1.48 0.46 5.45 7.60 4.60 4.35 7.95 4.75 0.60 4.00 1.80 2.00 4.80 1.85 3.87 5.40 1.30 3.30 3.20 3.20 a 6 7 notes: 6. shown centerline measurement of 0.46mm applies to zl9006m mod ule. for the zl9010m module, this measurement is 0.33mm. all ot her measures identical for both the zl9006m and zl9010m modules . 7. shown pad edge measurement of 3.87mm applies to zl9006m modul e. for the zl9010m module, this measurement is 3.60mm. all othe r measurements are identical for both the zl9006m and zl9010m modules.
zl9010m 71 fn8422.2 january 22, 2015 submit document feedback terminal and pad edge details bottom view 2.75 2.75 5.73 1.53 3.28 5.13 2.39 1.98 8.15 0.00 0.13 1.48 0.48 1.23 3.48 2.48 5.73 5.28 8.60 8.25 7.65 6.25 2.95 2.75 6.95 6.75 2.75 0.35 1.25 0.00 0.25 0.65 1.35 0.75 2.35 1.75 0.00 1.35 0.75 2.35 1.75 7.75 7.75 5.35 3.35 4.75 5.75 5.95 7.35 6.75 5.35 3.75 3.35 4.75 4.35 6.35 5.75 7.35 6.75 1.13 1.53 2.13 2.53 3.13 3.53 4.13 4.53 5.13 8.35 0.00 5.48 4.88 3.48 4.48 3.88 2.88 2.48 1.88 1.48 0.88 0.48 0.53 0.13 8.60 8.35 7.75 notes: 8. shown edge pad measurement o f 2.39mm applies to zl9006m modul e. for the zl9010m module, this measurement is 2.13mm. all othe r measurements are identical for both the zl9006m & zl9010m modules. 8
zl9010m 72 fn8422.2 january 22, 2015 submit document feedback 2.90 2.90 3.11 4.11 5.11 3.54 4.54 5.73 7.77 8.60 8.34 7.34 2.34 4.77 6.77 5.77 4.95 6.34 5.34 5.75 2.77 3.34 3.75 4.75 3.95 2.95 1.77 0.77 1.34 0.00 3.89 4.89 5.73 2.89 1.89 0.89 1.11 1.78 0.54 7.77 8.60 2.46 1.46 0.46 0.11 1.54 2.11 2.54 0.98 0.22 1.02 4.46 5.46 3.46 8.34 7.34 2.34 2.77 3.77 4.77 5.77 6.77 6.34 5.34 3.34 4.34 1.23 0.66 0.23 0.34 0.77 1.77 1.34 0.00 5.10 4.00 4.90 3.10 3.80 5.30 6.00 7.10 6.20 7.30 5.73 4.97 3.42 8.60 8.00 7.75 3.90 5.10 5.60 6.60 4.10 6.10 5.40 7.05 8.15 8.60 5.73 1.58 3.63 0.57 2.57 5.13 4.48 3.95 0.78 0.03 0.23 0.87 1.07 1.33 2.37 1.38 1.97 0.43 4.27 3.75 stencil opening edge position (for reference) top view 2.75 5.95 1.22 1.98 1.48 3.53 4.13 4.53 5.13 0.00 0.88 0.48 0.53 1.13 1.53 2.13 2.53 3.13 0.13 8.35 7.75 7.35 5.48 4.88 3.48 4.48 3.88 2.88 2.48 1.88 8.35 8.60 7.75 7.35 2.35 2.35 4.75 6.75 6.35 5.75 5.35 3.35 2.75 4.75 6.75 6.35 5.75 5.35 3.35 4.35 3.75 2.75 0.25 1.75 1.35 0.00 0.75 0.35 0.65 1.25 2.75 1.75 1.35 0.00 0.75 7.65 2.95 6.25 6.75 6.95 1.48 3.28 0.00 5.73 1.53 5.13 0.48 2.39 8.15 0.13 5.73 2.48 5.28 8.25 8.60 3.48 pcb land pattern (for reference) top view

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